Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In. IEEE Trans. VLSI Syst., 17(12):1730-1741, 2009. [doi]

@article{BahukudumbiC09-0,
  title = {Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In},
  author = {Sudarshan Bahukudumbi and Krishnendu Chakrabarty},
  year = {2009},
  doi = {10.1109/TVLSI.2008.2006679},
  url = {http://dx.doi.org/10.1109/TVLSI.2008.2006679},
  tags = {testing},
  researchr = {https://researchr.org/publication/BahukudumbiC09-0},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {17},
  number = {12},
  pages = {1730-1741},
}