Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In. IEEE Trans. VLSI Syst., 17(12):1730-1741, 2009. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.