An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/Throughput

Tianshuo Bai, Jingcheng Gu, Lehao Tan, Wente Yi, Haolin Ge, Han Zhang, Zhenyu Xue, He Zhang 0011, Na Lei, Biao Pan. An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/Throughput. In Design, Automation & Test in Europe Conference, DATE 2026, Verona, Italy, April 20-22, 2026. pages 1-7, IEEE, 2026. [doi]

Abstract

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