Table of Contents

• MIRAGE:MRAM-Based Near ADC-Less Compute-In-Memory Macro for Deep Learning AccelerationMainakh Mukherjee, Ayan B. Pranta, Utkarsh Saxena, Anushka Mukherjee, Deepika Sharma, Gaurav Kumar K, Kaushik Roy 0001. 1-7 [doi]
• FAQNAS: FLOPs-aware Hybrid Quantum Neural Architecture Search using Genetic AlgorithmMuhammad Kashif, Shaf Khalid, Alberto Marchisio, Nouhaila Innan, Muhammad Shafique 0001. 1-7 [doi]
• VeriRepair: Toward Reliable LLM-Based RTL Repair via CoT-Supervised Multi-Objective Fine-Tuning and Hybrid RetrievalLei Peng, Aijiao Cui, Yier Jin. 1-7 [doi]
• Focus Session: Exploring Semantic Leakage in Edge FPGA Implementations of Neural NetworksZhuoran Liu 0001, Konstantina Miteloudi, Durba Chatterjee, Lejla Batina. 1-7 [doi]
• Analysis and Mitigation of IR Drop in Memristor-based AI Hardware AcceleratorsEmmanouil Arapidis, Theofilos Spyrou, Konstantinos Stavrakakis, Emmanouil Anastasios Serlis, Moritz Fieback, Said Hamdioui, Anteneh Gebregiorgis. 1-3 [doi]
• SSALDPC: A Syndrome-Sum Based Adaptive LDPC Decoding Scheme for NAND Flash MemoryLanlan Cui, Fei Wu 0005, Yunlong He, Kun Jiang 0001, Yeqiu Xiao, Renzhi Xiao, Changsheng Xie 0001. 1-7 [doi]
• Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V SimulatorsKatharina Ruep, Manfred Schlägl, Daniel Große. 1-3 [doi]
• STAR: High-DoF Robotic Manipulation for Memory-Constrained NN AcceleratorJhao-Ying Chen, Wen Sheng Lim, Tei-Wei Kuo, Yuan-Hao Chang 0001. 1-7 [doi]
• TANGRAM: A Novel ILP-based On-Track Bus Routing via Placement and Compression of PolygonsJaekyung Im, Seokhyeong Kang. 1-6 [doi]
• MC-CGRA: A Memory-Computation Coordinated CGRA Framework for Stream ProcessingChen Shi, Chunhua Xiao, Han Diao, Weijie Yuan, Junling Wang. 1-6 [doi]
• SurgeQ: A Hybrid Framework for Ultra-Fast Quantum Processor Design and Crosstalk-Aware Circuit ExecutionXinxuan Chen, Hongxiang Zhu, Zhaohui Yang, Zhaofeng Su, Jianxin Chen, Feng Wu, Huihai Zhao. 1-7 [doi]
• LoRA-Edge: Tensor-Train-Assisted LoRA for Practical CNN Fine-Tuning on Edge DevicesHyunseok Kwak, Kyeongwon Lee, Jae-Jin Lee, Woojoo Lee. 1-7 [doi]
• 3D-ICE 4.0: Accurate and efficient thermal modeling for 2.5D/3D heterogeneous chiplet systemsKai Zhu, Darong Huang 0003, Luis Costero, David Atienza 0001. 1-7 [doi]
• Compact Yet Fast: An Efficient d-Order Masked Implementation of AsconMattia Mirigaldi, Nico Paninforni, Maurizio Martina, Guido Masera. 1-7 [doi]
• An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/ThroughputTianshuo Bai, Jingcheng Gu, Lehao Tan, Wente Yi, Haolin Ge, Han Zhang, Zhenyu Xue, He Zhang 0011, Na Lei, Biao Pan. 1-7 [doi]
• Shakan: Training-Inference co-design for Oblique Random Forests on Embedded DevicesAlessandro Annechini, Alessandro Verosimile, Marco D. Santambrogio. 1-7 [doi]
• 2RT: Efficient Ray Tracing Accelerator with Approximate-Accurate Computing and QuantizationZhiyuan Zhang, Zhihua Fan, Wenming Li, Yudong Mu, Yuhang Qiu, Zhen Wang 0045, Xiaochun Ye, Xuejun An. 1-7 [doi]
• Noise-Aware Adaptive Sampling for Robust Diffusion Models on Analog Compute-in-MemoryYuannuo Feng, Wenyong Zhou, Yuexi Lv, Hanjie Liu, Guangyao Wang, Zhengwu Liu, Ngai Wong 0001, Wang Kang 0001. 1-3 [doi]
• Gohan: A Golden-Copy-Aided Platform Enabling Online Hybrid-Interactive Reliability AnalysisQuan Cheng, Haoyuan Li, Wang Liao 0001, Feng Liang, Longyang Lin, Masanori Hashimoto. 1-7 [doi]
• Cyber-Physical System Design Space Exploration for Affordable Precision AgriculturePawan Kumar, Hokeun Kim. 1-7 [doi]
• No Pixel, More Efficient: Multimodal Framework for Sub-nm Mask Process CorrectionKai Ma, Tianyi Li, Jiaqi Liu, Jingyi Yu 0001, Hao Geng. 1-7 [doi]
• FlashGEMM: Mesh-Aware Efficient GEMM for 3D-Stacked LLM AcceleratorsXin Fan 0009, Chen Bai, Xin Yang, Zhenhua Zhu 0002, Yanhong Wang, Zhao Zhang 0001, Yuan Xie 0001. 1-7 [doi]
• PALM: Program Analysis and LLM Methods for Crafting SystemVerilog AssertionsRaheel Afsharmazayejani, Benjamin Tan 0001. 1-7 [doi]
• MX-SAFE: Versatile Inference-and Training-Proof Microscaling Format with On-the-Fly Exponent and Mantissa Bit AllocationDahoon Park, Jahyun Koo 0002, Sangwoo Hwang, Jaeha Kung. 1-7 [doi]
• Efficient Warpage Simulation of Complex 2.5-D/3-D IC Structures with Novel Meshing Algorithm and Layerwise Plate TheoryTianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang. 1-7 [doi]
• Attacking and Securing Hybrid Homomorphic Encryption Against Power AnalysisAikata Aikata, Maciej Czuprynko, Nedzma Musovic, Emira Salkic, Sujoy Sinha Roy. 1-7 [doi]
• Future Result Capture: Timing Anomalies Reveal Data from Instructions in the SuccessorRoua Boulifa, Marwa Chehab, Paolo Maistri, Giorgio Di Natale. 1-7 [doi]
• Data Distribution-Aware Analog/Digital Conversion Strategy for Energy-Efficient Memristive In-Situ AcceleratorsTaoming Lei, Heng Zhou, Bing Wu 0001, Wei Tong 0001, Dan Feng 0001. 1-3 [doi]
• Kolmogorov-Arnold Networks for Autonomous Driving: A Hardware-in-the-Loop Comparison with Conventional Deep Neural NetworksChaoran Yuan, Fadi J. Kurdahi. 1-7 [doi]
• GPU-Accelerated Efficient Transduction for Logic OptimizationZhuofan Lin, Shiju Lin. 1-7 [doi]
• Lupin: Spatial Resource Stealing with Outlier-First Encoding for Mixed-Precision LLM AccelerationTaein Kim, Sukhyun Han, Seongwook Kim, Gwangeun Byeon, Jungmin Lee, Seokin Hong. 1-3 [doi]
• Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA SynchronizationLorenzo Ruotolo, Giovanni Pollo, Mohamed Amine Hamdi, Matteo Risso, Yukai Chen, Enrico Macii, Massimo Poncino, Sara Vinco, Alessio Burrello, Daniele Jahier Pagliari. 1-3 [doi]
• ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSAQuinten Norga, Suparna Kundu, Ingrid Verbauwhede. 1-3 [doi]
• PQCUARK: A Scalar RISC-V ISA Extension for ML-KEM and ML-DSAXavier Carril, Alicia Manuel Pasoot, Emanuele Parisi, Oriol Farràs, Carlos Andres Lara-Nino, Miquel Moretó. 1-7 [doi]
• MD-SNN: Membrane Potential-aware Distillation on Quantized Spiking Neural NetworkDonghyun Lee 0002, Abhishek Moitra, Youngeun Kim, Ruokai Yin, Priyadarshini Panda. 1-7 [doi]
• Graph-SRAM: Efficient Graph Learning-based SRAM Simulation via Waveform PropagationBeisi Lu, Lihao Liu, Li Shang, Fan Yang 0001. 1-7 [doi]
• Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit GeneratorsRahul Kumar, Rohan Kumar, Borivoje Nikolic. 1-7 [doi]
• Late Breaking Results: Practical Power Side-Channel Attack on Analog Compute-in-Memory MacroSimon Wilhelmstätter, Johannes Stark, Devanshi Upadhyaya, Maël Gay, Ilia Polian, Maurits Ortmanns. 1-3 [doi]
• Parallel-SA: Point Cloud Processing Acceleration via Parallel Set AbstractionDongdong Tang, Weilan Wang, Yu Mao 0001, Wenjing Xie, Nan Guan, Tei-Wei Kuo, Chun Jason Xue. 1-7 [doi]
• MeshHD: Near-Linear Encoding for Hyperdimensional Computing via Multi-Scale Bases and Kronecker FactorizationWoongjae Han, Jiseung Kim, Hyukjun Kwon, Hojeong Kim, Selim An, Shinhyoung Jang, Yeseong Kim. 1-7 [doi]
• SecIC3: Customizing IC3 for Hardware Security VerificationQinhan Tan, Akash Gaonkar, Yu-Wei Fan, Aarti Gupta, Sharad Malik. 1-7 [doi]
• Submodular Maximization-inspired Adaptive Routing Bend Space PlanningSiting Liu 0002, Peng Xu 0052, Peiyu Liao, Keren Zhu 0001, Yibo Lin, Bei Yu 0001. 1-7 [doi]
• Ramen: Radiation-Aware Modeling Framework for PDK-Enabled Design and Library CharacterizationQuan Cheng, Haoyuan Li, Zhenzhe Chen, Wang Liao 0001, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin. 1-7 [doi]
• Multicore Design Verification Directed by Reinforcement LearningLuiz M. V. Pereira, Diego M. Meditsch, Guilherme O. Campos, Luiz C. V. dos Santos. 1-7 [doi]
• Multi-Partner Project: Quantum-Secure IoT-based Digital Manufacturing Pilot in QUBIP projectEros Camacho-Ruiz, Pablo Navarro-Torrero, Piedad Brox, Maria Chiara Molteni, Alberto Battistello, Davide Bellizia, Agostino Sette, Enrico Bisio, Nicola Tuveri, Enrico Bravi, Francesco Vaccaro, Grazia D'Onghia, Andrea Vesco. 1-6 [doi]
• Reshaping Bayesian Optimization for Design Space Optimization Towards Accurate and Irredundant Evaluation in EDA Tool Parameter ExplorationChanhee Jeon, Taewhan Kim 0001. 1-7 [doi]
• Optimization of AND-Gate-Sparse Circuit Synthesis for Multi-party Computation Systems with Local CommunicationsYinfan Zhao, Makoto Ikeda. 1-3 [doi]
• KirbyMM: Outer-Product Based Matrix Multiplication on ARMv9 ProcessorLanshu Huang, Han Huang, Zhiguang Chen 0001, Yutong Lu. 1-7 [doi]
• Late Breaking Results: Efficient Formal Verification of Highly Optimized MAC UnitsJan Kleinekathöfer, Lennart Weingarten, Kamalika Datta, Rolf Drechsler. 1-3 [doi]
• Scalable Second-Order Optimizer for Full-Chip Inverse Lithography TechniquesSu Zheng, Ziyang Yu 0001, Bei Yu 0001, Martin D. F. Wong. 1-7 [doi]
• HEED: A Highly Efficient Electromagnetic Fault Detection SchemeRoukoz Nabhan, Mohammad Ebrahimabadi, Jean-Luc Danger, Jean-Max Dutertre, Sylvain Guilley, Naghmeh Karimi, Raphael Viera 0001, Iyad Zaarour. 1-7 [doi]
• A Multi-Sensor Approach for Soft Labeling in Human Activity Recognition DomainMatteo Iervasi, Cristian Turetta, Florenc Demrozi, Graziano Pravadelli. 1-7 [doi]
• Focus Session: Large Language Models in Physical Design: From Data Generation to Intelligent AgentsBing-Yue Wu, Atmadip Dey, Austin Rovinski, Vidya A. Chhabria. 1-7 [doi]
• Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set ExtensionSongqiao Cui, Geng Luo, Junhan Bao, Josep Balasch, Ingrid Verbauwhede. 1-7 [doi]
• COFFEE: A Carbon-Modeling and Optimization Framework for HZO-based FeFET eNVMsHongbang Wu, Xuesi Chen, Shubham Jadhav, Amit Lal, Lillian Pentecost, Udit Gupta 0001. 1-7 [doi]
• SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial IntelligenceSaoud Aldowaish, Yashwanth Karumanchi, Kai-Chen Chiang, Soroosh Noorzad, Morteza Fayazi. 1-3 [doi]
• DyGen: A Constant-Time Kernel Generator for Dynamic-Shape Neural NetworksYuhan Kang, Wenrui Zhang, Dong Chen 0015, Yang Shi 0008, Jianchao Yang, Zeyu Xue, Jing Feng, Mei Wen. 1-7 [doi]
• A Low-Power Bayesian Head Using SOT-MRAM Arrays for Uncertainty-Aware Binary Neural NetworksJoao Henrique Quintino Palhares, Bruno Lovison Franco, Louis Hutin, Jonathan Miquel, Kamel-Eddine Harabi, Aymen Romdhane, Kevin Garello. 1-7 [doi]
• From Trigger to Impact: Knowledge-Graph Reasoning and Risk-Aware Classification for Hardware Trojan DetectionYang Zhang 0026, Xing Hu 0012, Xiaowen Chen, Huan Guo, Zhenyu Zhao, Sheng Liu. 1-2 [doi]
• 3D IC Thermal Management with BEOL Wafer-Scale Sputtered Vertical h-BNCesely Smith, B. Reese, A. Raut, Y.-T. Yang, J.-G. Zhu, Tathagata Srimani. 1-7 [doi]
• Late Breaking Results: Quamba-SE: Soft-edge Quantizer for Activations in State Space ModelsYizhi Chen, Ahmed Hemani. 1-3 [doi]
• Accurate Analytical Modeling for NoCs with Hybrid Arbitration under High Traffic InjectionRahul Tripathy, Mohammad Majharul Islam, Riad Akram, Raid Ayoub, Sumit K. Mandal. 1-7 [doi]
• RouterAcc: FPGA Acceleration for VLSI Detailed Router via Hierarchical Storage MappingRuiyuan Guo, Zexu Zhang, Chang Liu, Da Tang, Weiqi Shen, Haodong Lu, Xiqiong Bai, Kun Wang, Jianli Chen, Jun Yu. 1-7 [doi]
• An Environment-Aware Verification Framework for LLM-Generated Robot Control ProgramsZhanShang Nie, Wenbo Wang, Xuanming Liu, Yue Zhang, Zhendong Chen, Zirui Wang, Kai Huang, Shuai Zhao. 1-7 [doi]
• EEMU: A FEMU-based Accurate, Parametric Ethernet-SSD EmulatorXikun Jiang, Chao Li, Tianyu Wang 0009, Xiaowei Chen, Zhaoyan Shen, Zili Shao. 1-2 [doi]
• HoPart: Hop-Constrained Partitioning with Routing Support for Multi-FPGA SystemsYuan Huang, Longkun Guo, Weijie Fang, Jiawei Lin. 1-7 [doi]
• EDA Flow Matters: Stage-Aware Parameter Optimization of Tool ChainXinheng Li, Donger Luo, Peng Xu 0052, Ziyang Yu 0001, Qi Sun 0002, Tinghuan Chen, Bei Yu 0001, Hao Geng. 1-7 [doi]
• Optimal Compilation of Syndrome Extraction Circuits for General Quantum LDPC CodesKai Zhang, Dingchao Gao, Zhaohui Yang, Runshi Zhou, Fangming Liu, Zhengfeng Ji, Jianxin Chen. 1-7 [doi]
• Smart Imager with Object Detection Exploiting Edge-Frame-Base Processing and Bounding Box Extraction for μW Power Purely-Harvested Sensor NodesHayate Okuhara, Udari De Alwis, Liu Yue, Karim Ali Ahmed, Massimo Alioto. 1-7 [doi]
• Dynamic Algorithm Configuration for Global PlacementChen Lu, Ke Xue 0001, Ruo-Tong Chen, Yunqi Shi, Siyuan Xu, Mingxuan Yuan, Chao Qian 0001, Zhi-Hua Zhou. 1-7 [doi]
• VLIM: Verified Loop Interchange for Optimised Matrix MultiplicationOliver Turner, Shounak Chakraborty 0001. 1-7 [doi]
• Entropy Sampling-Based Neural Architecture Search for Resource-Constrained Microcontroller TargetsChristian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich. 1-7 [doi]
• SFQ-Based CJoin Gate Implementation for Ultra-Low-Power Brownian Logic CircuitsSoshi Takagi, Masamitsu Tanaka, Koji Inoue, Satoshi Kawakami. 1-7 [doi]
• FSDB: A Folded-Store Dynamic-Broaden Hybrid Compute-in-ROM/SRAM Architecture for Deploying Large-Scale DNNs On-ChipTianyi Yu, Teng Yi, Huazhong Yang, Xueqing Li 0002. 1-7 [doi]
• GMaC: NvCIM Architecture for Parallel Point-based Point Cloud Acceleration via Geometric Mapping and Address-Index ComputationYi Gao, Zongwei Wang 0001, Ling Liang, YiMao Cai. 1-7 [doi]
• AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS DesignsYingxin Zeng, Binghao Cheng, Jianwang Zhai, Kang Zhao, Zhe Lin 0001. 1-7 [doi]
• MAPLE: Modality-Aware Projection-free LiDARCamera Fusion for 3D Vehicular Object DetectionAbhishek Balasubramaniam, Sudeep Pasricha. 1-3 [doi]
• A Parallel Mixed-Precision GMRES-IR Solver for Ill-Conditioned Equations in Device SimulationJiawen Cheng, Yuanyuan Yang, Ding Gong, Wenjian Yu. 1-7 [doi]
• HINT: A Hybrid SRAM-MRAM Compute-In-Memory with INput-aware Skipping SAR-ADC for Energy Efficient Ternary LLMsJaebeom Park, Seung-Eon Hwang, Jongsun Park. 1-7 [doi]
• TSIM4ICS: Trace-Driven SystemC-TLM Simulation Framework for I/O Die-Based Multi-Chiplet SystemsYoungchul Yoon, Soonhoi Ha. 1-7 [doi]
• Architecture, Design and Technology Co-optimization for 3D ICs with Advanced BSPDN Considering Power & Thermal Integrity ImpactHu Zhou, Haolan Yang, Xingcheng Liu, Linqiu Wang, Feifan Xie, Yumeng Wang, Zhuojun Chen, Zhiyong Zhang, Lianmao Peng, Rongmei Chen. 1-7 [doi]
• Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code GenerationM. Zafir Sadik Khan, Kimia Zamiri Azar, Hadi Mardani Kamali. 1-7 [doi]
• Identifying Hardware Optimizations for Neural Network Inference using Virtual PrototypesJan Zielasko, Rolf Drechsler. 1-7 [doi]
• Efficient Image Reconstruction Architecture for Neutral Atom Quantum ComputingJonas Winklmann, Yian Yu, Xiaorang Guo, Korbinian Staudacher, Martin Schulz 0001. 1-3 [doi]
• Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToTZhiteng Chao, Yonghao Wang, Xinyu Zhang, Jiaxin Zhou, Tenghui Hua, Husheng Han, Tianmeng Yang, Jianan Mu, Bei Yu 0001, Rui Zhang 0040, Jing Ye 0001, Huawei Li 0001. 1-7 [doi]
• Late Breaking Results: Never-Stopping Inference: Self-Healing AI Accelerators on SRAM-FPGAsEleonora Vacca, Giorgio Cora, Luca Sterpone. 1-3 [doi]
• SCARLET: A Scalable OPCM-Based Accelerator for Transformer Inference with Tiled CrossbarsSina Karimi, Guowei Yang 0005, Carlos A. Ríos Ocampo, Ajay Joshi, Ayse K. Coskun. 1-7 [doi]
• Circuit-Aware Analysis of Arithmetic Error Detection CodesCheng Chiu, Keyon Mazandarani, Nathan Bleier. 1-3 [doi]
• A Collaborative Framework for Multi-Level Multi-Objective Design Space ExplorationJiangnan Li, Kaixiang Zhu, Yuping Bai, Yunfei Dai, Qing He, Yu He, Lingli Wang. 1-7 [doi]
• Physical-Aware eFPGA Redaction for Secure and Efficient Hardware IP ProtectionYunqi He, You Li 0008, Ruofan Huang, Guannan Zhao, Hai Zhou 0001. 1-7 [doi]
• Dynamic Rank-Aware Aggregation with Graph Contrastive Learning for Federated Foundation Model Fine-TuningZhao Yang 0005, Xunyun Qiu, Hua Cui. 1-7 [doi]
• Toward Parallel Serving for Vision-Language Models via Modal Decoupling and SchedulingYijia Yang, Yubo Deng, Yida Wang, Yuanchao Xu, Keni Qiu. 1-7 [doi]
• Exploiting Variable-Dimensional LDPC Coding to Improve NAND Flash Memory System PerformanceMeng Zhang 0014, Wei Li 0312, Yangyi Li, Tianwei Gui, Changsheng Xie 0001, Fei Wu 0005. 1-7 [doi]
• Vmxdotp: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format AccelerationMax Wipfli, Gamze Islamoglu, Navaneeth Kunhi Purayil, Angelo Garofalo, Luca Benini. 1-7 [doi]
• X-Sim: An Accurate and Scalable Simulator for Memristive Computing-in-Memory AcceleratorsKonstantinos Stavrakakis, Bas Smeele, Emmanouil Arapidis, Theofilos Spyrou, Anteneh Gebregiorgis, Stephan Wong, Georgi Gaydadjiev, Said Hamdioui. 1-7 [doi]
• Optimize edge AI processing through innovative compilation techniquesShreya Alladi, Alexandre Lopoukhine, Georgios Alexandris, Andrea Nardi-Dei, Ravikiran Ravindranath Reddy, Christos P. Lamprakos, Panagiotis Chaidos, Alexis Maras, Alberto Ros 0001, Tobias Grosser, Sotirios Xydis, Dimitrios Soudris, Marc Geilen, Sander Stuijk, Henk Corporaal, Alexandra Jimborean. 1-7 [doi]
• 3D Integration of Hybrid IGZO/Si and IGZO eDRAMs for High-Density/High-Performance On-Chip MemoryMunhyeon Kim, Sukhyun Choi, Yulhwa Kim, Jae-Joon Kim. 1-7 [doi]
• PatBiNN: A 65 nm Processing-in-CAM Based BNN Implementation for Pathogen Genome ClassificationYuval Harary, Almog Sharoni, Esteban Garzón, Leonid Yavits. 1-7 [doi]
• DAPO: Design Structure-Aware Pass Ordering for HLS via Contrastive and Reinforcement LearningJinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu 0001, Wei Zhang 0012. 1-7 [doi]
• A Mathematical Exploration to Equivalence Checking of Quantum CircuitsYou-Cheng Lin, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Chia-Chieh Chu, Chun-Yao Wang. 1-3 [doi]
• CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic RepresentationsYonghao Wang, Yang Yin, Hongqin Lyu, Jiaxin Zhou, Zhiteng Chao, Mingyu Shi, Wenchao Ding 0007, Yunlin Du, Jing Ye 0001, Tiancheng Wang, Huawei Li 0001. 1-3 [doi]
• NuRedact: Non-Uniform eFPGA Architecture for Low-Overhead and Secure IP RedactionVoktho Das, Kimia Zamiri Azar, Hadi Mardani Kamali. 1-7 [doi]
• Artemis: Co-Simulation of Power Microgrids and Energy-Aware Cloud Data CentersMattia Tibaldi, Sara Vinco, Christian Pilato. 1-7 [doi]
• Accelerating Detailed Routing Convergence through Offline Reinforcement LearningAfsara Khan, Austin Rovinski. 1-7 [doi]
• Smart-PCLib: A LLM-based Multi-Agent Framework for Automated PCB Component Library GenerationZhaohai Di, Jindong Tu, Zhiyuan He, Yuan Pu 0001, Jiawei Liu 0006, Chong Tong, Tsung-Yi Ho, Bei Yu 0001, Tinghuan Chen. 1-7 [doi]
• How to Manage the Mapping Table of Large-Capacity Solid-State DrivesYang Zhou 0037, Fang Wang 0001, Dan Feng 0001. 1-7 [doi]
• Drafting and Multi-Input Switching in Digital Dynamic Timing Simulation for Multi-Input GatesArman Ferdowsi, Ulrich Schmid 0001, Josef Salzmann. 1-3 [doi]
• Multi-Partner Project: Scheduling-Deployment Workflow for Autonomous RoboRacer Driving Stacks in the HAL4SDV ProjectMatthias Stammler, Henrik Scheidt, Tanja Harbaum, Jürgen Becker 0001, Konstantin Dudzik, Victor Pazmino Betancourt, Federico Gavioli, Paolo Burgio, Arvind Easwaran, Andreas Eckel. 1-7 [doi]
• Multi-Partner Project: CeCaS Accelerator Design for Efficient Supercomputing in Automotive SystemsAnnina Gutermann, Alexey Serdyuk, Fabian Lesniak, Julian Höfer, Hella Toto-Kiesa, Tanja Harbaum, Jürgen Becker 0001, Brian Pachideh, Sven Nitzsche, Moritz Neher, Carmen Weigelt, Jann Krausse, Victor Pazmino Betancourt, Klaus Knobloch, Lukas Groth, Andrija Neskovic, Saleh Mulhem, Mladen Berekovic. 1-7 [doi]
• IncreMacro-3D: Incremental Macro Placement for Face-to-Face Stacked Memory-on-Logic 3D ICsLancheng Zou, Sing Sen Ye, Shuo Yin, Yuan Pu 0001, Jiaxi Jiang, Siting Liu 0002, Yuxuan Zhao 0001, Bei Yu 0001. 1-7 [doi]
• Focus Session: Stepping Stones Towards Domain Acceleration Using AI-Driven High-Level Synthesis DesignStefan Abi-Karam, Miaoyan Zhou, Cong Callie Hao. 1-6 [doi]
• Towards learning-based gate-level glitch analysisAnastasis Vagenas, Dimitrios Garyfallou, Georgios I. Stamoulis. 1-3 [doi]
• 3D Chiplet Partitioning and Floorplanning Interaction with Vertical Bonding ConsiderationTong Shen, Mengen Chen, Xu He, Yao Wang 0002, Yang Guo 0003. 1-7 [doi]
• Hyperplane Input Space Cuts for Neural Network VerificationJonathan Hjort, Ahmed Rezine. 1-7 [doi]
• DEEP-LENS: Deep-Learning Powered Layout Extraction and Novel Segmentation for IC Assurance and SecurityShuvodip Maitra, Abhishek Chakraborty 0001, Debdeep Mukhopadhyay. 1-7 [doi]
• Zion: A Comprehensive, Adaptive, and Lightweight Hardware PrefetcherVadim Biryukov, Xiaoyang Lu, Zirui Liu 0001, Kaixiong Zhou, Xian-He Sun. 1-7 [doi]
• Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System SimulationXuguang Yuan, Jiangyuan Gu, Qidie Wu, Yang Hu 0001, Shaojun Wei, Shouyi Yin. 1-3 [doi]
• Dolphium: Co-Optimizing Quantization Dataflow and Paradigms on Poly-Hierarchical NPUsXiuping Cui, Chengrui Zhang, Xiang Chen, Yun (Eric) Liang. 1-7 [doi]
• Automatic Extraction of Timing Models for WCET Estimation From a High-Level Synthesis FlowThomas Feuilletin, Dylan Leothaud, Simon Rokicki, Steven Derrien, Isabelle Puaut. 1-7 [doi]
• Black-Box Robustness Probing of Graph Neural Networks for VLSI Circuit NetlistsRupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu. 1-7 [doi]
• Late Breaking Results: A Power-Efficient RISC-V Baseband System-on-Chip for Multi-Standard Integrated Sensing and CommunicationsLimin Jiang, Yi Shi 0004, Yihao Shen, Yintao Liu 0001, Siyi Xu, Qingyu Deng, Xiaoxiao Chen, Qianli Wang, Shan Cao 0001, Zhiyuan Jiang, Sheng Zhou 0001. 1-3 [doi]
• Efficient Down-sampling in Hybrid Neural Networks using Adversarial AutoencodersJonghyeon Nam, Joonseok Kim, Eunji Kwon, Seokhyeong Kang. 1-3 [doi]
• Focus Session: What the Fuzz! Pushing Beyond Randomness in Hardware Security with Generative AINikhilesh Singh, Mohamadreza Rostami, Lichao Wu, Chen Chen 0125, Stephen Muttathil, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi. 1-7 [doi]
• Compacted-LUT: Fine-Grained Customizable LUT Architecture via SRAM-MUX Co-OptimizationMingyang Chen, Yunfei Dai, Wai-Shing Luk, Qing He, Yu He, Lingli Wang. 1-7 [doi]
• TrustSeed: Lightweight Attestation Protocol for Ensuring LLM IntegrityMohamed Alsharkawy, Mohamed Aboelenien Ahmed, Hassan Nassar, Jeferson González-Gómez, Heba Khdr, Osama Abboud, Xun Xiao, Jörg Henkel. 1-7 [doi]
• SPOILER-GUARD: Gating Latency Effects of Memory Accesses through Randomized Dependency PredictionGayathri Subramanian, Girinath P, Nitya Ranganathan, Kamakoti Veezhinathan, Gopalakrishnan Srinivasan. 1-3 [doi]
• IterQuant: Iterative Quantization Framework for Mixed-Precision LLM CompressionHyungyo Jeong, Jiwoo Kim, Hyeokjun Kwon, Jaeho Lee, Youngjoo Lee. 1-7 [doi]
• FARM: Fast Acceleration of Random forests via in-Memory traversalAymen Ahmed, Valeria Bertacco. 1-7 [doi]
• Efficient Arithmetic on FPGADanila A. Gorodecky, Leonel Sousa. 1-2 [doi]
• NX-CGRA: A Programmable Hardware Accelerator for Core Transformer Algorithms on Edge DevicesRohit Prasad. 1-7 [doi]
• SATA: Sparsity-Aware Scheduling for Selective Token AttentionZhenkun Fan, Zishen Wan, Che-Kai Liu, Ashwin Sanjay Lele, Win-San Khwa, Bo Zhang, Meng-Fan Chang, Arijit Raychowdhury. 1-7 [doi]
• Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation ModelsMuhammad Shafique 0001, Abdul Basit 0013, Muhammad Abdullah Hanif, Alberto Marchisio, Rachmad Vidya Wicaksana Putra, Minghao Shao. 1-7 [doi]
• FALCON-3D: Full-Chip Analytical Thermal Simulation with Lateral CONvection for 3D-Stacked ICsTsung-Lin Lu, Yu-Min Lee, Pei-Yu Huang, Ching-Hsiang Wang. 1-7 [doi]
• AURORA - AUtomated 8T SRAM Wired-OR Logic Array for Boolean-Based Machine LearningKomal Krishnamurthy, Marcos L. L. Sartori, Shengyu Duan, Alex Yakovlev, Rishad A. Shafik. 1-7 [doi]
• UniSEC: A Unified Security Evaluation Framework for Secure Cache ArchitecturesPratik Shrestha, Achim D. Brucker, M. Khurram Bhatti. 1-7 [doi]
• FHEx: Transforming Generic Compute Chips into Secure FHE Engines via a Hardware-software Co-designed FrameworkYibo Du, Ying Wang 0001, Mengdi Wang 0004, Cangyuan Li, Lian Liu, Hui Li, Kai Zhang, Yinhe Han 0001. 1-7 [doi]
• ChatTest: Coverage-Enhanced Testbench Generation for Agile Hardware Verification with LLMsGwok-Waa Wan, Shengchu Su, Jingyi Zhang, Sam-Zaak Wong, Mengnv Xing, Lei Ji, Zhe Jiang 0004, Xi Wang 0009, Jun Yang 0006. 1-7 [doi]
• DRVision: A DRV-aware Routability Optimization Framework with Multi-modal Prediction and Vision-Based Routing GuidanceXu Cheng, Pengcheng Fan, Peng Cao. 1-7 [doi]
• Timing-driven Detailed Placement via TimingMask-guided Path-level OptimizationRuo-Tong Chen, Chengrui Gao, Siyuan Xu, Ke Xue 0001, Yunqi Shi, Xi Lin 0001, Mingxuan Yuan, Chao Qian 0001, Zhi-Hua Zhou. 1-7 [doi]
• LogHD: Robust Compression of Hyperdimensional Classifiers via Logarithmic Class-Axis ReductionSanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, Pietro Mercati, Nathaniel D. Bastian, Mohsen Imani. 1-7 [doi]
• CD-PIM: A High-Bandwidth and Compute-Efficient LPDDR5-Based PIM for Low-Batch LLM Acceleration on Edge-DeviceYe-Lin, Chao Fang, Xiaoyong Song, Qi Wu, Anying Jiang, Yichuan Bai, Li Du. 1-7 [doi]
• FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AIEun-Su Cho, Jongin Choi, Jeongmin Jin, Jae-Jin Lee, Woojoo Lee. 1-7 [doi]
• Optimizing Multibit Flip-Flop Banking via Agile In-Placement PPA Co-OptimizationHuan-Yuan Chen, Yu-Ruei Lin, Mark Po-Hung Lin, Hung-Ming Chen. 1-3 [doi]
• HPPlacer: A High-Precision Slack-Aware Global Placement EngineQinggong Shen, Chaoli Zhang, Haoyang Xu, Zhiwen Yu 0001, Bin Guo 0001, Yuxuan Zhao 0001, Bei Yu 0001, Tsung-Yi Ho, Xing Huang 0001. 1-7 [doi]
• Anchor-and-Adapt: HLS QoR Prediction using Ground-Truth Seeding and Few-Shot Fine-TuningGabriel C. Tavares, Heitor C. De Andrade, Fábio P. Itturriet, Gabriel L. Nazar. 1-7 [doi]
• A Low Power and High Reliability Nonvolatile SRAM Using In-Plane VGSOT-MRAM with Pre-Charge Restore SchemeXiaoyang Xu, Chenyi Wang, Zhongzhen Tong, Mingche Li, Weimeng Zhao, Zhongkui Zhang, Yaling Wang, Chao Wang 0094, Zhaohao Wang. 1-7 [doi]
• Provable Guarantees in Approximate SynthesisKushagra Gupta, Priyanka Golia, Subhajit Roy 0001, Kuldeep S. Meel. 1-7 [doi]
• PPA-driven Placement via Adaptive Cluster Constraints OptimizationZiyan Liu, Siyuan Xu, Jie Wang 0005, Zijie Geng, Yeqiu Chen, Mingxuan Yuan, Jianye Hao, Feng Wu 0001. 1-7 [doi]
• Multi Partner Project: STRATUM, co-creation protocol and advanced smart GUI for a 3D neurosurgery supporting toolEmanuele Torti, Himar Fabelo, Elisa Marenzi, Maria Luisa Alvarez-Male, Chrysanthi Bairaktari, Beatriz Noriega-Ortega, Raquel León, Santiago Marco, Asaf Badouh, Max Verbers, Carlos Vega, Javier Santana-Nunez, Yolanda Ramallo-Fariña, Christian Weis, Ana M. Wägner, Eduardo Juárez 0001, Claudio Rial, Alfonso Lagares, Gustav Burström, Luis Jimenez-Roldan, Teresa Cervero, Miquel Moretó, Giovanni Danese, Svitlana Zinger, Francesca Manni, Miguel A. García-Bello, Lidia García, Jesús Morera, Juan F. Piñeiro, Bernardino Clavo, Francesco Leporati, Gustavo M. Callicó. 1-7 [doi]
• XTree on EquiMesh: Topology and Algorithm Co-Design for Collective CommunicationJunwei Cui, Le Qin, Weilin Cai, Jiayi Huang 0001. 1-7 [doi]
• Multi-Partner Project: Enhancing Resilience, Efficiency, and Trustworthiness of Edge AI in Safety-Critical Systems (GuardAI)Antonis D. Savva, Mehmet Demirel, Yeshwanth Kumar Adimoolam, Rafaella Elia, Alexandros Gkillas, Christos Anagnostopoulos, Erion-Vasilis M. Pikoulis, Amalia Damianou, Charmaine Barker, Daniel Bethell, Ahmed Salah Tawfik Ibrahim, Filippo Cugini, Francesco Paolucci, Kyriakos Vlachos, Simos Gerasimou, Antonios Lalas, Konstantinos Votis, Aris S. Lalos, Christos Kyrkou, Theocharis Theocharides. 1-7 [doi]
• MemoryIslands: A Federated Approach for Efficient Memory MappingsFatemeh Derakhshani, Mohamed Hassan. 1-7 [doi]
• SMIX: Schedulable Instruction Set Architecture Extension Interface for Multi-Operand OperatorsShufan He, Hanmo Wang, Kefa Chen, Xuyin Chen, Xianhua Liu, Chun Yang. 1-3 [doi]
• COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural EventsMahmudul Hasan 0012, Sudipta Paria, Swarup Bhunia, Tamzidul Hoque. 1-7 [doi]
• Scalable Symbolic Reasoning with Matrix-Based Brain-Inspired Representations and Vector-Space AccelerationWilliam Youngwoo Chung, Hyunwoo Oh, Hamza Errahmouni Barkam, Calvin Yeung 0002, Mohsen Imani. 1-3 [doi]
• MACAM: A Flexible Computing-in-Memory Accelerator for Sparse Matrix-Dense Vector MultiplicationXiaoyu Zhang 0009, Rui Liu 0045, Zerun Li, Yinhe Han 0001, Xiaoming Chen 0003. 1-7 [doi]
• An Efficient Weight Correction Method to Recover Non-ideal Errors in Pruned IRC DesignsShih-Han Chang, Yi-Min Pan, Chong-En Hong, Chien-Nan Jimmy Liu. 1-3 [doi]
• Multi-partner project: Ecodesign to reduce electronic wasteChiara Sandionigi, Olivia Belorgeot, Elise Chaumat, Jean-Christophe Crebier, George Dimitrakopoulos 0001, Lena Froger, Thomas Krivec, Michel Monsellier, Lucas Pinto, Ioannis V. Vondikakis, Christof Wernbacher, Edmund Whitmore, Olivier Pedoussaut. 1-7 [doi]
• Sensor Placement and Transformer-Based Thermal Map Generation for Reusable InterposersAristotelis Tsekouras, Theodoros Papavasileiou, Panagiotis C. Petrantonakis, Georgios Keramidas, Vasilis F. Pavlidis. 1-7 [doi]
• GCPT: Gradient-aware Clustering Method for Efficient Post-Training Quantization in Large Neural NetworksChuyi Dai, Chen Ye, ZeYu Li, Jun Tao, Wei Zhang, Grace Li Zhang, Xin Li. 1-7 [doi]
• ACES: A Chiplet Architecture with Resource Partition and Dynamic Scheduling for Agentic LLMsHongou Li, Mingxuan Li, Zhantong Zhu, Tianyu Jia. 1-7 [doi]
• When Faults Don't Vanish: Persistent Fault Injection and Key Recovery on MRAM-Backed AESBrojogopal Sapui, Priyanjana Pal, Mehdi B. Tahoori. 1-7 [doi]
• HILAL: Hessian-Informed Layer Allocation for Heterogeneous Analog-Digital InferenceAniss Bessalah, Hatem Mohamed Abdelmoumen, Karima Benatchba, Hadjer Benmeziane. 1-7 [doi]
• Multi-Partner Project: UP2DATE4SDV : Enabling Safe and Secure Modular Updates, Upgrades and Dynamic Task-Reallocation and -Execution for Software Defined VehiclesGregor Nitsche, Patrick Uven, Hannes Fuchs, Enrico Mezzetti, Marcus Hähnel, Mijangos Ane, Kim Grüttner. 1-7 [doi]
• MGPA: A Memristor-based Genome Processing Accelerator for Single-cell RNA SequencingYang Han, Lianfeng Yu, Teng Zhang, Bowen Wang, Yihang Zhu, Lei Cai, Yaoyu Tao, Yuchao Yang 0001. 1-3 [doi]
• Node2Node: Node Adaptation with Transformer for Cross-Node Hotspot DetectionWenbo Xu, Silin Chen, Yibo Huang 0009, Xinyun Zhang, Zixiao Wang, Bei Yu 0001, Ningmu Zou. 1-7 [doi]
• Colored Huge Pages: A Hardware-Software Approach for Enhanced Isolation and PerformanceGeorgios-Alexandros Kostas, Dimitris Gizopoulos, Vasileios Karakostas. 1-7 [doi]
• Machine Learning-Driven Early Performance Prediction Framework for Accelerated Microarchitecture SimulationAiden Stickney, Osvaldo Castro, Aaron Chan, Paul V. Gratz, Jiang Hu 0001, Aakash Tyagi, Jered Dominguez-Trujillo, Galen M. Shipman, Kevin Sheridan. 1-7 [doi]
• FastRW: An Efficient Random Walk Method for Steady-State Thermal AnalysisZixiao Wang, Tianshu Hou, Chenghan Wang, Zhen Zhuang, Tsung-Yi Ho, Farzan Farnia, Bei Yu 0001. 1-3 [doi]
• RAPID-Graph: Recursive All-Pairs Shortest Paths Using Processing-in-Memory for Dynamic Programming on GraphsYanru Chen, Zheyu Li, Keming Fan, Runyang Tian, John Hsu, Weihong Xu, Minxuan Zhou, Tajana Rosing. 1-7 [doi]
• Late Breaking Results: Input Loss Curvature as a Predictor of Sample Vulnerability to Hardware-NoiseDeepika Sharma, Deepak Ravikumar, Chih-Hsing Ho, Sangamesh Kodge, Kaushik Roy 0001. 1-3 [doi]
• Lithography Hotspot Detection for Complex Non-Manhattan Layouts via Graph Neural NetworkBoHao Li, Ranran Liu, Yumeng Liu, Cong Jiang, Kang Liu 0017, Bei Yu 0001, Kun Ren, Qi Sun 0002, Cheng Zhuo. 1-6 [doi]
• FedCM: Fine-grained Kernel Scheduling and Management to Improve GPU SharingXianWei Zhang, Xuanteng Huang, Nong Xiao 0001. 1-7 [doi]
• High-Performance and High-Density NAND-Like SOT-MRAM for FinFET Technology NodesChao Wang 0094, Xianzeng Guo, Luman Xiang, Zhaohao Wang, Weisheng Zhao 0001. 1-3 [doi]
• LATIAS: A General Architecture-Operator Model for Spatial Accelerators with Complex Topology and Memory HierarchyChengrui Zhang, Liancheng Jia, Chu Wang, Tianqi Li, Renze Chen, Xiuping Cui, Size Zheng 0001, Shengen Yan, Xiuhong Li, Yu Wang 0002, Xiang Chen, Yun (Eric) Liang. 1-7 [doi]
• Reinforcement Learning for Hybrid Bonding Terminal Legalization in 3D ICsWanqi Ren, Chengrui Gao, Yunqi Shi, Mingzhou Fan, Siyuan Xu, Ke Xue 0001, Chenjian Ding, Mingxuan Yuan, Chao Qian 0001. 1-3 [doi]
• RheoSparse: Exploring Finer Grained Structured Sparsity for Small Language ModelsJianing Zheng, Gang Chen. 1-7 [doi]
• C-STEP: Compute-Efficient Spiking Transformers with Temporal Exit and Early-Guided PruningKyungchul Lee, Jongsun Park. 1-3 [doi]
• AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device OptimizationGuangxi Fan, Tianliang Ma, Xuguang Sun, Xun Wang, Kain Lu Low, Leilai Shao. 1-7 [doi]
• Agentic AI for Digital Wellness: Challenges and Architectural Perspectives for Smart Home CareLuigi Capogrosso, Francesco Biondani, Francesca Bigardi, Stefano Cordibella, Giovanni Perbellini, Walter Vendraminetto, Franco Fummi. 1-3 [doi]
• Efficient CNN Inference on Ultra-Low-Power MCUs via Saturation-Aware ConvolutionShiming Li, Luca Mottola, Yuan Yao 0009, Stefanos Kaxiras. 1-3 [doi]
• Focus Session: Advanced CMOS and 5.5D Packaging: Perspectives and Challenges for Design, Reliability and SecurityHussam Amrouch, Dragomir Milojevic, Giorgio Di Natale, Jérôme Toublanc. 1-6 [doi]
• A Real-Time Robotic Diffusion Policy Accelerator Exploiting Self- and Cross-Guided Modal SimilarityBoju Chen, Xiaoyu Feng, Junyan Lin, Chen Tang, Huazhong Yang, Yongpan Liu. 1-7 [doi]
• Exact Synthesis with Optimal Switching ActivityMarcel Walter, Michael Feldmeier, Robert Wille. 1-7 [doi]
• LAMP: An Adaptive Near-Memory Processing System for High-Performance Long-Read MappingJo-Ling Huang, Liang-Chi Chen, Chien-Chung Ho, Yuan-Hao Chang 0001. 1-7 [doi]
• MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QAZhenghao Chen, Yuan Pu 0001, Hairuo Han, Yuntao Nie, Jiajun Qin, Yuhan Qin, Tairu Qiu, Zhuolun He, Jianwang Zhai, Bei Yu 0001, Kang Zhao. 1-7 [doi]
• NITRO: 3D NAND Flash-Based In-Storage LLM Computing with Enhanced Activation DataflowSanghun Shin, Gisan Ji, Sungju Ryu. 1-3 [doi]
• Efficient LLM Decoding on Ryzen AI NPUsZhenyu Xu, Miaoxiang Yu, Jillian Cai, Qing Yang 0001, Tao Wei 0001. 1-7 [doi]
• Late Breaking Results: Algorithm-Hardware Co-Design of a Sparsity-Aware Dense-Sparse Scheme for DNN AcceleratorsYueting Li 0001, Zhen Li, Terry Tao Ye, Weisheng Zhao 0001. 1-2 [doi]
• Evaluation of Thermal and Power integrity and its Impact on Performance for 3D Memory-on-Logic CPUs with FSPDN and BSPDNYumeng Wang, Xincheng Liu, Hu Zhou, Linqiu Wang, Haolan Yang, Zhuojun Chen, Zhiyong Zhang, Lianmao Peng, Rongmei Chen. 1-3 [doi]
• BOLD-Q: Blockwise Outlier-aware Logarithmic Dual-Bias Quantization for Hardware-Efficient LLM InferenceSungsoo Han, Dahun Choi, Hyun Kim. 1-7 [doi]
• A Graph-Theoretic Framework for Randomness Optimization in First-Order Masked CircuitsDilip Kumar S. V., Benedikt Gierlichs, Ingrid Verbauwhede. 1-7 [doi]
• eLogic: An E-Graph-based Logic Rewriting Framework for Majority-Inverter GraphsRongliang Fu, Wei Xuan, Shuo Yin, Guangyu Hu, Chen Chen 0001, Hongce Zhang, Bei Yu 0001, Tsung-Yi Ho. 1-6 [doi]
• Make it Darker: A Gray Code Popcounter to Protect BNN CIM Against Power AttacksFouwad Jamil Mir, Asmae El Arrassi, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil. 1-7 [doi]
• GPU Acceleration of the Sum-Check Protocol Over Towers of Binary Fields for Verifiable ComputingAndrew Fan, Yanze Wu, Harry Han, Md Tanvir Arafin. 1-7 [doi]
• IP-Matcher: An Efficient One-to-Many Matching Framework for Analog Circuit Design and ReusingShixin Chen, Peng Xu 0052, Yapeng Li, Tinghuan Chen, Bei Yu 0001. 1-7 [doi]
• Formal Methods-Assisted Chosen Ciphertext Attacks on PQC CRYSTALS-Kyber Using Electromagnetic EmanationsYashaswini Makaram, Davis Ranney, A. Adam Ding, David Kaeli, Yunsi Fei. 1-7 [doi]
• PRISM: A Locality-Aware Near-Memory Processing Framework for Scalable Triangle CountingShangtong Zhang, Xueyan Wang, Yier Jin. 1-7 [doi]
• CIRCE CROSS Integrated RISC-V Cryptographic ExtensionAlessandra Dolmeta, Valeria Piscopo, Maurizio Martina, Guido Masera. 1-3 [doi]
• RATuner: Retrieval-Augmented VLSI Flow Design Parameter Tuning FrameworkPeng Xu 0052, Ziyang Yu 0001, Yuan Pu 0001, Xinyun Zhang 0001, Donger Luo, Hao Geng, Siyuan Xu, Tsung-Yi Ho, Bei Yu 0001. 1-7 [doi]
• QSLM: A Performance- and Memory-aware Quantization Framework with Tiered Search Strategy for Spike-driven Language ModelsRachmad Vidya Wicaksana Putra, Pasindu Wickramasinghe, Muhammad Shafique 0001. 1-7 [doi]
• RISC-V ISA Extensions for Vectorized Unstructured Sparse SpMM in LLM InferenceTengfei Xia, Zhihua Fan, Jing Xue, Shantian Qin, Xiaochun Ye, Wenming Li. 1-7 [doi]
• RETRO: Mitigating Power Side-Channel Attacks with Reconfigurable RFET-based Ring OscillatorsNima Kavand, Tushar Niranjan, Armin Darjani, Akash Kumar 0001. 1-7 [doi]
• LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) VerificationMd. Ajoad Hasan, Dipayan Saha, Khan Thamid Hasan, Nashmin Alam, Azim Uddin, Sujan Kumar Saha, Mark Tehranipoor, Farimah Farahmandi. 1-7 [doi]
• Multi-Partner Project: Efficient Deep Learning Platforms for Next-Generation Embedded Edge-AI SystemsRajendra Bishnoi, Mohammad Amin Yaldagard, Konstantinos Stavrakakis, Said Hamdioui, Kanishkan Vadivel, Pankaj Upadhyay, Nicolas Daniel Rodriguez, Teresa van Dam, Sander Steeghs-Turchina, Agathe Archet, Prathamesh Satish Deshpande, Giovanni Grandi, Hana Krichene, William Fabre, Fabian Chersi. 1-7 [doi]
• PICoSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN AccelerationBowen Duan, Zhenhua Zhu 0002, Zhengyang Duan, Huazhong Yang, Yuan Xie 0001, Yu Wang 0002. 1-7 [doi]
• Scytale: A Compiler Framework for Accelerating TFHE with Circuit BootstrappingRostin Shokri, Nektarios Georgios Tsoutsos. 1-7 [doi]
• Focus Session: LLM4PQC - Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMsBuddhi Perera, Zeng Wang, Weihua Xiao, Mohammed Nabeel 0001, Ozgur Sinanoglu, Johann Knechtel, Ramesh Karri. 1-7 [doi]
• Eunomia: Preemption-based and QoS-aware Core Allocation in Oversubscribed CloudYunda Guo, Puqing Wu, Haoqiong Bian, Yunpeng Chai, Yao Shen, Haoyu Yang, Qing Liu, Zhengbin Huang, Le Yue, Yi Yang. 1-7 [doi]
• Multi-Partner Project: Multi-GPU Performance Portability Analysis for CFD Simulations at ScalePanagiotis-Eleftherios Eleftherakis, George Anagnostopoulos, Anastassis Kapetanakis, Mohammad Umair, Jean-Yves Vet, Konstantinos Iliakis, Jonathan Vincent, Jing Gong, Akshay Patil, Clara García-Sánchez, Gerardo Zampino, Ricardo Vinuesa, Sotirios Xydis. 1-6 [doi]
• RIFT: A Scalable Methodology for LLM Accelerator Fault Assessment using Reinforcement LearningKhurram Khalil, Muhammad Mahad Khaliq, Khaza Anuarul Hoque. 1-7 [doi]
• SuperPhys-Net: A Physics-Informed Super-Resolution Electromagnetic Simulator for Nanophotonic DevicesYiyang Su, Hao Chen, Guohao Dai, Yuzhe Ma, Yeyu Tong. 1-7 [doi]
• MPM-LLM4DSE: Reaching the Pareto Frontier in HLS with Multimodal Learning and LLM-Driven ExplorationLei Xu, Shanshan Wang, Chenglong Xiao. 1-7 [doi]
• Validating Formal Hardware Specifications Through Generated Behavioral ModelsRobert Kunzelmann, Zeyad Tahoun, Vinod Bangalore Ganesh, Maximilian Berger, Emil Baerens, Wolfgang Ecker. 1-7 [doi]
• A Formally Verified Secure Caching Mechanism on TrustZone-enabled MicrocontrollersSalvatore Bramante, Matteo Busi 0001, Alessandro Cilardo, Riccardo Focardi, Flaminia L. Luccio, Stefano Mercogliano. 1-3 [doi]
• RAMP: RTL-Level Emulation with Thousand-Core-Scale ParallelismWeigang Feng, Yijia Zhang, Zekun Wang, Zhengyang Wang, Yi Wang, Peijun Ma, Ningyi Xu. 1-7 [doi]
• Simulator-Driven Deep Reinforcement Learning for Analog Circuit DesignFelicia B. Guo, Ken T. Ho, Andrei Vladimirescu, Borivoje Nikolic. 1-7 [doi]
• MONET: A Mixture-of-Experts Accelerator with a Multicast-Optimized Two-Tier Network-on-ChipSiqin Liu, Maya Roediger, Avinash Karanth. 1-7 [doi]
• Exploring a Resource-Efficient NTT FPGA Accelerator for Fully Homomorphic EncryptionValentino Guerrini, Giuseppe Sorrentino, Davide Conficconi. 1-3 [doi]
• AutoPMS: A Framework for Automated Power Management System Design via Hierarchical Modeling and Embedded Design KnowledgeBin Ye, Shuo Li. 1-7 [doi]
• Dynamic Voltage, Body Bias and Frequency Scaling for FD-SOI-Based Low-Power Edge ProcessorsShrihari Gokulachandran, Navneet Jain, Andreas Gerstlauer. 1-7 [doi]
• FLARE: Finetuning ReLU With FIRE for Efficient Long-Context InferenceMichael Moffatt, Junyi Luo, Haoran Cheng, Qilong Wang, Xinting Jiang, Guanchen Tao, Shiwei Liu 0002, Kauna Lei, Gregory Kielian, Mehdi Saligane. 1-7 [doi]
• Software-Based Approximate Multiplication on Multiplierless CPUs Using Custom InstructionShalu Prathmesh Rajiv, Rajesh Kedia. 1-7 [doi]
• DynaMo: Runtime Switchable Quantization for MoE with Cross-Dataset AdaptationZihao Zheng, Xiuping Cui, Size Zheng 0001, Maoliang Li, Jiayu Chen, Yun Liang 0001, Xiang Chen. 1-7 [doi]
• ACEMARL: Adaptive Clustering Enhanced Multi-Agent Reinforcement Learning for Analog Circuit SizingHan Wu, Haoning Jiang, Zhuoli Ouyang, Ziheng Wang, Qi Shen, Bo Yuan, Yan Lu 0002, Junmin Jiang. 1-7 [doi]
• Simultaneous Multithreading and Common-Period Sporadic Tasks in Hard Real-TimeSims Hill Osborne. 1-7 [doi]
• A Digital Neural Array IC for Real-Time Neural Network Replication from Spike ActivitiesDonghyun Park, Hajung Mun, Minhyeok Jeong, Dahee Kang, Jongmin Lee 0001, Yoonmyung Lee. 1-7 [doi]
• LiveVerilogEval: Contamination Free and Automatically Scalable Benchmark for Verilog Code GenerationCharles Young, Hao Yu 0016, Dezhi Ran, Qingchen Zhai, Tianqi Qiu, Frank Qu, Bangyan Wang, Yuan Xie 0001, Tao Xie 0001. 1-7 [doi]
• Near-Optimal TDM Ratio Assignment for Die-Level Routing in Multi-FPGA SystemsJiawei Lin, Longkun Guo, Weijie Fang. 1-7 [doi]
• ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic FamilySeo Hyun Kim, Minhyeok Jeong, Jongmin Lee. 1-7 [doi]
• A Reliability-Physics-Based Approach for Data Tampering Detection in Commercial 3D-NAND Flash MemoryYuhan Wang, Jian Huang, Ruibin Zhou, Yao Liu, Haotian Ye, Xianping Liu. 1-7 [doi]
• PatchBlock: A Lightweight Defense Against Adversarial Patches for Embedded EdgeAI DevicesNandish Chattopadhyay, Abdul Basit 0013, Amira Guesmi, Muhammad Abdullah Hanif, Bassem Ouni, Muhammad Shafique 0001. 1-7 [doi]
• Boosting the Performance of Tree-Based Speculative Decoding of LLMs on FPGAsTielong Liu, Gang Li 0015, Zitao Mo, Zeyu Zhu, Minnan Pei, Jian Cheng 0001. 1-7 [doi]
• Postponing the Glitches is not Enough A Critical Analysis of the DATE 2024 E-ISW Masking SchemeAmir Moradi 0001. 1-3 [doi]
• A Scheduling Framework for Efficient MoE Inference on Edge GPU-NDP SystemsQi Wu, Chao Fang, Jiayuan Chen, Ye-Lin, Yueqi Zhang, Yichuan Bai, Yuan Du, Li Du. 1-7 [doi]
• Late Breaking Results: SP-HD: Stochastic Projection-Based HyperDimensional Architecture for Near-Sensor Image ClassificationAhmed Mamdouh, Sabrina Hassan Moon, Abu Kaisar Mohammad Masum, Emilien Meyer, Sercan Aygun, Dayane Reis. 1-3 [doi]
• Re-RIS: A Reconfigurable 3D RRAM In-Sensor Architecture for Low-Latency Machine VisionShiyang Li, Lixia Han, Siyuan Chen, Lifeng Liu, Peng Huang 0004. 1-3 [doi]
• Enhance Language Model-based Repair for Memory-related Vulnerabilities via Knowledge-and Semantic-guided AnalysisHao Shen 0002, Ming Hu 0003, Yanxin Yang, Xiaofei Xie, Mingsong Chen 0001. 1-7 [doi]
• DecoHD: Decomposed Hyperdimensional Classification under Extreme Memory BudgetsSanggeon Yun, Hyunwoo Oh, Ryozo Masukawa, Mohsen Imani. 1-7 [doi]
• Provably Optimal Planar Pareto Nearest Neighbor Search with Double Monotone ChainsZizheng Guo 0001, Runsheng Wang, Yibo Lin. 1-7 [doi]
• From Forest to Tree: Prioritizing the Maximum Additional Delay in AQFP Circuit DesignYinuo Bai 0002, Mingjia Fan, Tsung-Yi Ho, Zhou Jin 0001. 1-3 [doi]
• TRACE: A Transferable Framework for Aging-aware Cell Delay EstimationMuyan Jin, Chao Yang, Yunlin Liu, Zejian Cai, Pengpeng Ren, Zhigang Ji. 1-7 [doi]
• RASNIL: PVT-Robust Many-Objective Analog Sizing via Nested Hybrid Fidelity Framework with Incremental LearningXingyu Tang, Sen Yin, Zhujun Yao, Bingzhang Huang, Xiaosen Liu, Yan Wang 0023. 1-7 [doi]
• The PMP Snapshot Engine: Fast and Fault-Resilient PMP Reconfiguration for RISC-VChristian Larmann, Abdullah Aljuffri, Adrian Marotzke, Alejandro Garza, Said Hamdioui, Mottaqiallah Taouil. 1-7 [doi]
• ARCSyn: Aging-Aware Accuracy-Reconfigurable Logic SynthesisRuicheng Dai, Feiyang Shu, Pengpeng Ren, Runsheng Wang, Weikang Qian. 1-3 [doi]
• FLICKER: A Fine-Grained Contribution-Aware Accelerator for Real-Time 3D Gaussian SplattingWenhui Ou, Zhuoyu Wu, Yipu Zhang, Dongjun Wu, Frederick Ziyang Hong, C. Patrick Yue. 1-7 [doi]
• DiffResist: Physics-Constrained Diffusion for Photoresist ModelingZixiao Wang, Jieya Zhou, Xinyun Zhang, Shoubo Hu, Farzan Farnia, Bei Yu 0001. 1-3 [doi]
• Synthesizable PUF Design with Library Characterization for Secure Storage in Edge DevicesYuseong Lee, Donghyun Park, Jang-Hyun Kim, Jongmin Lee. 1-3 [doi]
• OpenACM: An Open-Source SRAM-Based Approximate CiM CompilerYiqi Zhou, Junhao Ma, Xingyang Li, Yule Sheng, Yue Yuan, Yikai Wang, Bochang Wang, Yiheng Wu, Shan Shen, Wei Xing, Daying Sun, Li Li, Zhiqiang Xiao. 1-7 [doi]
• DynaOpt: A Heterogeneous Logic Optimization Framework with Dynamic Sequence GenerationXingyu Qin, Guande Dong, Jianwang Zhai, Kang Zhao. 1-7 [doi]
• Mixed-Precision Training and Compilation for RRAM-based Computing-in-Memory AcceleratorsRebecca Pelke, Joel Klein, José Cubero-Cascante, Nils Bosbach, Jan Moritz Joseph, Rainer Leupers. 1-7 [doi]
• FHEIns: Fully Homomorphic Encryption Acceleration for Large Data Applications with In-Storage ProcessingXuan Wang 0040, Tianqi Zhang, Keming Fan, Augusto Vega, Minxuan Zhou, Tajana Rosing. 1-7 [doi]
• RLConcolic: Enhancing Concolic Testing via Multi-Step Reinforcement LearningYan Tan, Xiangchen Meng, Yangdi Lyu. 1-7 [doi]
• The Munich Quantum Software Company: Developing Production-ready Quantum Computing SoftwareRobert Wille, Marcel Walter, Simon Toni Hofmann, Patrick Hopf, Marc Messing, Lukas Burgholzer. 1 [doi]
• QUILL: An Algorithm-Architecture Co-Design for Cache-Local Deformable AttentionHyunwoo Oh, Hanning Chen, Sanggeon Yun, Yang Ni 0001, Wenjun Huang 0001, Tamoghno Das, Suyeon Jang, Mohsen Imani. 1-7 [doi]
• Design and Optimization of Solar-Powered Embedded Systems with Uppaal StrategoIsmael Samaye, Abdoulaye Gamatié. 1-3 [doi]
• PREFACE: Proactive Re-executions for Fault-aware Mixed-criticality EnvironmentsHwisoo So, Byeonggil Jun, Chanhee Lee 0002, Hokeun Kim, Aviral Shrivastava. 1-7 [doi]
• ETLA-3D: Equivalent Thin Layer Aggregation based Thermal FEM for Hybrid Bonding F2F 3D ICsChenghan Wang, Zhen Zhuang, Kai Zhu, Darong Huang 0003, Luis Costero, Rongmei Chen, David Atienza 0001, Tsung-Yi Ho. 1-7 [doi]
• Design for testability using mixed-polarity flip-flops and latchesLorenzo Lagostina, Jordi Cortadella, Mario R. Casu, Luciano Lavagno. 1-6 [doi]
• Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible WearablesTheofanis Vergos, Polykarpos Vergos, Mehdi B. Tahoori, Georgios Zervakis 0001. 1-7 [doi]
• On Oracle-Guided Random Circuit Learning via Stochastic Boolean SatisfiabilityShakil Ahmed, Kaveh Shamsi. 1-7 [doi]
• Ultra-Low Logical Depth Fault-Tolerant Quantum Circuit Synthesis via Lattice SurgeryChien-Tung Cherie Kuo, Cheng-En Tsai, Chung-Yang Ric Huang. 1-7 [doi]
• CISim: ISA-Agnostic Custom Instruction Simulation for General-Purpose ProcessorXiaoyu Hao, Sen Zhang, Liang Qiao, Jun Shi 0007, Junshi Chen 0003, Hong An. 1-7 [doi]
• BADGE: Boundary-Aware Dirichlet Graph Embedding for Initialization in DREAMPlaceJaemin Park, Taejin Paik. 1-3 [doi]
• LiteDVS: A Low-Data-Redundancy Dynamic Vision Sensor with Hybrid Readout and In-Pixel DenoisingZichen Kong, Zhongyi Wu, Xiyuan Tang, Yuan Wang 0001. 1-7 [doi]
• LaMoS: Enabling Efficient Large Number Modular Multiplication through SRAM-based CiM AccelerationHaomin Li 0002, Fangxin Liu, Chenyang Guan, Zongwu Wang, Li Jiang 0002, Haibing Guan. 1-7 [doi]
• SA-ANT: Efficient Low-Bit Group-Wise Quantization for Large Language Models via Sign-Asymmetric Adaptive Numeric TypeXinkuang Geng, Siting Liu 0001, Hui Wang 0023, Jie Han 0001, Honglan Jiang. 1-7 [doi]
• SONIC: Smart Optimization for Neural-Integrated CMP with Timing-Aware FillsJiajun Tan, Qichao Ma, Yiming Du, Yiming Gan, Ling Lang, Yibo Lin, Ming Zhu, Zongwei Wang 0001, YiMao Cai. 1-3 [doi]
• T-MSA: Transformer-Driven Multi-Strategy Adaptive Microarchitecture Design Space ExplorationJingjing Wang, Zihan Lin, Fan Yang 0032, Xiaochuan Li 0001, Runze Zhang, Cong Xu 0001, RenGang Li, Baoyu Fan. 1-7 [doi]
• Multi-Partner Project: Outcomes of the ICSC Flagship 2 Project on Architectures and Design Methodologies to Accelerate AI WorkloadsCristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Cristian Zambelli, Sebastiano Fabio Schifano, Francesco Conti 0001, Angelo Garofalo, Luca Benini, Maurizio Palesi, Giuseppe Ascia, Enrico Russo 0002, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri, Fabio Frustaci. 1-7 [doi]
• T-SAR: A Full-Stack Co-design for CPU-Only Ternary LLM Inference via In-Place SIMD ALU ReorganizationHyunwoo Oh, KyungIn Nam, Rajat Bhattacharjya, Hanning Chen, Tamoghno Das, Sanggeon Yun, Suyeon Jang, Andrew Ding, Nikil D. Dutt, Mohsen Imani. 1-7 [doi]
• Contract-Based Architecture Exploration of Cyber-Physical Systems via Satisfiability Modulo Convex ProgrammingYifeng Xiao, Pierluigi Nuzzo 0002. 1-7 [doi]
• DS-CIM: Digital Stochastic Computing-In-Memory Featuring Accurate OR-Accumulation via Sample Region Remapping for Edge AI ModelsKunming Shao, Liang Zhao, Jiangnan Yu, Zhipeng Liao, Xiaomeng Wang, Yi Zou, Tim Kwang-Ting Cheng, Chi-Ying Tsui. 1-7 [doi]
• GE-LLM: Graph-Enhanced Large Language Models for Efficient Transistor-Level Circuit SimulationChao Wang 0120, Dan Niu, Yichao Dong, Dekang Zhang, Changyin Sun 0001, Zhou Jin 0001. 1-7 [doi]
• Focus Session: Accelerating Diffusion Models for Generative AI Applications with Silicon PhotonicsTharini Suresh, Salma Afifi, Sudeep Pasricha. 1-7 [doi]
• HAP: Accelerating DNNs with Resolution-Preserved Quantization by Harnessing Adaptive-PrecisionErjing Luo, Xinkuang Geng, Honglan Jiang, Leibo Liu, Jie Han 0001. 1-3 [doi]
• An IR drop-robust Mapping Method for Reliable Memristive AcceleratorsJinpeng Liu, Shiyi Song, Bing Wu 0001, Huan Cheng, Heng Zhou, Xueliang Wei, Wei Tong 0001, Dan Feng 0001. 1-7 [doi]
• Breaking Standard Cell Margin Constraints for Area-Efficient VLSI DesignJunghyun Yoon, Jooyeon Jeong, Heechun Park. 1-7 [doi]
• Open-Source Framework for Secure Hardware Design with Simulation-based Leakage AssessmentPablo Navarro-Torrero, Francisco J. Rubio-Barbero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox Jiménez. 1-3 [doi]
• Advancing LUT-based Threshold Logic Synthesis with Enhanced Area EstimationYu-Shan Lin, Yung-Chih Chen. 1-7 [doi]
• Soft-Error Resilient MRAM-OTP BCAM for DDR4 STT-MRAM Redundancy ManagementHaoran Du, Hongjin Zhu, Zhenghan Fang, Shuyu Wang, Hao Cai 0001. 1-7 [doi]
• DSR: A Systematic Approach for Efficient Double-sided Signal RoutingJianqing Chen, Zhenkun Lin, Xun Jiang 0002, Genggeng Liu, Yibo Lin, Gang Du. 1-7 [doi]
• Increasing the Efficiency of Associative Processor Architectures via CMOS-Compatible HybridizationSocrates S. Wong, Cecilio C. Tamarit, Mohammad Mehdi Sharifi, Zephan M. Enciso, Dayane Reis, Michael T. Niemier, X. Sharon Hu, José F. Martínez. 1-7 [doi]
• Equivalent-0ns-Replacement Self-Aware-Access LLC on Dual-Port SOT-MRAM by Sense-While-ReplaceKeyang Zhang, Quanhai Zhu, Zhenghan Fang, Shuyu Wang, Hao Cai 0001. 1-7 [doi]
• Diagnostic Test Generation for Fault Localization in Printed Neuromorphic CircuitsTara Gheshlaghi, Alexander Studt, Priyanjana Pal, Dina A. Moussa, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. 1-3 [doi]
• Population coding to improve fault tolerance of neuromorphic networks in regression tasksAlexis Gleyo, Bernard Girau. 1-7 [doi]
• FORWORD: Accelerating Formal Datapath Verification via Word-Level SweepingZiyi Yang, Guangyu Hu, Xiaofeng Zhou, Mingkai Miao, Changyuan Yu, Wei Zhang 0012, Hongce Zhang. 1-7 [doi]
• AERO: Adaptive and Efficient Runtime-Aware OTA Updates for Energy-Harvesting IoTWei Wei 0060, Jingye Xu, Sahidul Islam, Dakai Zhu 0001, Chen Pan, Mimi Xie. 1-7 [doi]
• Towards Trustworthy LLM-Based Assertion Generation: A Data Augmentation Framework with Formal Check ApproachQingchen Zhai, Hao Yu 0016, Chen Bai, Charles Young, Frank Qu, Dezhi Ran, Yuan Xie 0001, Tao Xie 0001. 1-7 [doi]
• Multi-Partner Project: Scalable, Ferroelectric-based Accelerators for Energy Efficient Edge AI (Ferro4EdgeAI)Theofilos Spyrou, Yashvardhan Biyani, Konstantinos Stavrakakis, Rajendra Bishnoi, Said Hamdioui, Joel Minguet Lopez, Louise Dumas, Jean Coignus, Denys Ly, Hugo Chazot-Ranquet, Laurent Grenouillet, Fabien Grimaud, Simon Martin 0006, Olivier Billoint, François Andrieu, Ruben Alcala, Stefan Slesazeck, Athira Sunil, Chong Peng, Antoine Cauquil, Rosario Pronsat, Damien Deleruyelle, Cédric Marchand 0002, Alberto Bosio, Ian O'Connor, Giulio Urlini, Simon Jeannot, Mohammad Sajedi Alvar, Nima Akbari Moghaddam, Thilo Werner, Tony Schenk, Bojun Cheng, Mina Khoei, Lucía Pérez Ramírez, Eunjin Koh, Somnath Kale, Nicholas Barrett. 1-7 [doi]
• Compression Space Search: RL-Based Combinational Compression for Neural NetworksYingtao Shen, Yinchen Ni, Jiace Zhu, Jie Zhao, An Zou. 1-7 [doi]
• Special Day - A Design Blueprint for Scalable Multi-Agent Architectures in Complex EDA WorkflowsValerio Tenace, Pierre-Emmanuel Gaillardon. 1-7 [doi]
• Special Day - GUIDE: GenAI Units In Digital Design EducationWeihua Xiao, Jason Blocklove, Matthew DeLorenzo, Johann Knechtel, Ozgur Sinanoglu, Kanad Basu, Jeyavijayan Rajendran, Siddharth Garg, Ramesh Karri. 1-7 [doi]
• SNIFFER: RL-based Vendor-Agnostic Test Case Generation for Triggering Long-Latency BehaviorsMingyu Pi, Michael Yun, Jaeseung Seok, Sangmin Kim, Sunghee Lee, Jinhwa Lee, Yoon Hyeok Lee. 1-7 [doi]
• Multi-Partner Project: COIN-3D - Collaborative Innovation in 3D VLSI ReliabilityGeorge Rafael Gourdoumanis, Fotoini Oikonomou, Maria Pantazi-Kypraiou, Pavlos Stoikos, Olympia Axelou, Athanasios Tziouvaras, Georgios Karakonstantis, Tahani Aladwani, Christos Anagnostopoulos 0001, Yixian Shen, Anuj Pathania, Alberto García Ortiz, George Floros 0002. 1-6 [doi]
• Enhanced CXL Pooled Memory System for Scalable AI via Embedding Access PredictionJongho Park, Hoyeon Lee, Seohyun Kim, Minho Ha, Byungil Koh, Jungmin Choi, Yeseong Kim. 1-7 [doi]
• Late Breaking Results: Conversion of Neural Networks into Logic Flows for Edge ComputingDaniel Stein, Shaoyi Huang, Rolf Drechsler, Bing Li 0005, Grace Li Zhang. 1-3 [doi]
• TT-Edge: A Hardware-Software Co-Design for Energy-Efficient Tensor-Train Decomposition on Edge AIHyunseok Kwak, Kyeongwon Lee, Kyeongpil Min, Chaebin Jung, Woojoo Lee. 1-7 [doi]
• Learning to Approximate: Circuit Learning and Deep Reinforcement Learning for Approximate Logic Synthesis with an Error Rate GuaranteeChi-Wei Chen, Yi-Ting Li, Wuqian Tang, Yung-Chih Chen, Jian-Meng Yang, Chun-Yao Wang. 1-7 [doi]
• Late Breaking Results: Boosting Efficient Dual-Issue Execution on Lightweight RISC-V CoresLuca Colagrande, Luca Benini. 1-3 [doi]
• Focus Session: Do Agentic LLMs Change the Paradigm of Hardware Test Generation?Farshad Firouzi, Pragya Sharma, Agastya Seth, Peter Domanski, Bahareh J. Farahani, Sanmitra Banerjee, Jonti Talukdar, Krishnendu Chakrabarty. 1-7 [doi]
• Towards Input-Distribution-Aware Approximate Multiplier Generation for CNNsAlessandro Buccolini, Marco Biasion, Rodrigo Otoni, George A. Constantinides, Laura Pozzi 0001. 1-3 [doi]
• FaTRQ: Tiered Residual Quantization for LLM Vector Search in Far-Memory-Aware ANNS SystemsTianqi Zhang, Flavio Ponzina, Tajana Rosing. 1-7 [doi]
• SCALER: A Stream-Aware Accelerator with Hierarchical Memory for Sparse LU Factorization on HBM FPGAsXin Xu, Zhiying Zhu, Zishu Li, Dan Niu, Cheng Zhuo, Zhou Jin 0001. 1-7 [doi]
• Quantum Circuit Synthesis Based on LimTDDXin Hong, Chenjian Li, Aochu Dai, Runhong He, Shenggang Ying. 1-7 [doi]
• SSR: Sparse Segment Reduction for Ternary GEMM AccelerationAdeline Pittet, Shien Zhu, Valérie Verdan, Gustavo Alonso. 1-7 [doi]
• Area Efficient Speculative Loop Pipelining for High-Level SynthesisDylan Leothaud, Simon Rokicki, Steven Derrien, Isabelle Puaut. 1-7 [doi]
• Quantum Hardware-Efficient Selection of Auxiliary Variables for QUBO FormulationsDamian Rovara, Lukas Burgholzer, Robert Wille. 1-7 [doi]
• A High-Performance Neural Rendering Accelerator Based on Novel Multi-Level Ray Scheduling and Dual-Process BackendWenkai Zhou, Yuefeng Zhang, Cheng Zhang, Binzhe Yuan, Junsheng Chen, Luntian Zhang, Xiangyu Zhang 0002, Pingqiang Zhou, Jingyi Yu 0001, Xin Lou 0001. 1-3 [doi]
• KAN-SAs: Efficient Acceleration of Kolmogorov-Arnold Networks on Systolic ArraysSohaib Errabii, Olivier Sentieys, Marcello Traiola. 1-7 [doi]
• MIQARA: Mixed-Criticality Queue-based Architecture for Reconfigurable Accelerator PlatformsHassan Nassar, Martin Rapp, Lars Bauer, Mostafa Elshimy, Zeynep Demirdag, Jörg Henkel. 1-7 [doi]
• Explainable GNN-Driven Test Point Insertion on Uncontrollable I/OsSung-Hyuk Cho, Tae-Min Park, Jeongyeol Lee, Jae-Youn Hong, Andreas Gerstlauer, Joon-Sung Yang. 1-7 [doi]
• Late Breaking Results: RL-Based Macro Placement with Cell Clustering and Rudy Modeling for Routability OptimizationYouwen Wang, Hao Gu, Xinglin Zheng, Keyu Peng, Ziran Zhu. 1-3 [doi]
• Multi-Partner Project: Advancing European Semiconductor and Chiplet Innovation Through the Bavarian Chip Design CenterHussam Amrouch, Jehaan Joseph, Michael Schirmer, Johannes Geier, Ulf Schlichtmann, Michael Meidinger, Thomas Wild, Andreas Herkersdorf, Jens Nöpel, Georg Sigl, Yicheng Zhang, Carsten Trinitis, Aswathy Nedumpalli Sankaranarayanan, Martin Schulz 0001, Andreas Korb, Konrad Hohentanner. 1-7 [doi]
• Quantum Circuit Compilation for Superconducting Bus-Resonator ArchitecturesPatrick Hopf, Lukas Burgholzer, Robert Wille. 1-7 [doi]
• PCB-Migrator: Automated PCB PnR MigrationYaohui Han, Beichen Li 0003, Rongliang Fu, Qunsong Ye, Zhiyuan Lu, Junchen Liu, Bei Yu 0001, Tsung-Yi Ho, Tinghuan Chen. 1-7 [doi]
• StreamNTT: A High-Throughput, HLS-Based Streaming NTT Accelerator for HBM-Equipped FPGAsYoung Kyu Choi, Hyunwoo Park, Wei He, Sunwoong Kim. 1-7 [doi]
• Focus Session Paper: The MQT Compiler Collection : A Blueprint for a Future-Proof Quantum-Classical Compilation FrameworkLukas Burgholzer, Daniel Haag, Yannick Stade, Damian Rovara, Patrick Hopf, Robert Wille. 1-7 [doi]
• Beaivi: A 22-nm 1-GHz+ Exposed Datapath RISC-V DSP for Low-Power ApplicationsKari Hepola, Joonas Multanen, Väinö-Waltteri Granat, Jakub Zádník, Roope Keskinen, Karri Palovuori, Pekka Jääskeläinen. 1-7 [doi]
• CAMI: A Context-Aware Isolation Architecture for GPU MemoriesHao Lan, Wei Yan 0005, Qinfen Hao, Xiaochun Ye, Yier Jin, Yong Liu, Ninghui Sun. 1-7 [doi]
• FLAME: A Framework Exploring Execution Strategies for Multi-Cycle Operations in CGRAJiajun Qin, Cheng Tan 0002, Ruihong Yin, Tianhua Xia, Sai Qian Zhang, Bei Yu 0001. 1-7 [doi]
• MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code GenerationNowfel Mashnoor, Mohammad A. Makhzan, Hadi Kamali, Kimia Zamiri Azar. 1-7 [doi]
• Efficient Federated Learning with Low-Rank Updates under Homomorphic EncryptionMohamed Aboelenien Ahmed, Mohamed Alsharkawy, Hassan Nassar, Heba Khdr, Jeferson González-Gómez, Jörg Henkel. 1-7 [doi]
• Input Sparsity Aware In-Memory Computing Macro Based on SOT-MRAM Multi-Level Cell for Efficient Deep Neural Network AccelerationChao Wang 0094, Qihang Gao, Xianzeng Guo, Zhongzhen Tong, Zhaohao Wang, Weisheng Zhao 0001. 1-7 [doi]
• Late Breaking Results: Thermally Assisted RowPress-RowHammer Synergy for Cross-Row Bit FlipsFilip Roth Trønnes-Christensen, Ranyang Zhou, Gamana Aragonda, Abeer Matar A. Almalky, Mohaiminul Al Nahian, Adnan Siraj Rakin, Shaahin Angizi. 1-3 [doi]
• Interpretable Graph Neural Networks for Fault Detection in Circuit NetlistsRupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu. 1-3 [doi]
• FSR-GeMM: A Scalable FSR-Parallel Photonic Accelerator for Real-Valued GeMM ComputingPeiyu Chen, Yinyi Liu, Minhang Xu, Chongyi Yang, Xiaohan Jiang, Wei Zhang 0012, Jiang Xu 0001. 1-7 [doi]
• Breaking the BRAM Wall: Scalable Vina FPGA Acceleration via Distributed Grid Storage and Cross-Board Long-Ring PipelinesAnkun Tian, Shidi Tang, Ruiqi Chen 0001, Ming Ling. 1-7 [doi]
• GRAIN: A Design-Intent-Driven Analog Layout Migration FrameworkBingyang Liu, Haoning Jiang, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, David Z. Pan, Yibo Lin. 1-3 [doi]
• MISP-Net: Significantly Reducing Transient Backward Steppings via Novel Multi-step Irregular Sequence PredictionYichao Dong, Dan Niu, Chao Wang 0120, Zhenya Zhou, Zhou Jin 0001, Changyin Sun 0001. 1-7 [doi]
• Late Breaking Results: PolyRAD - Polynomial Formal Verification of Restoring Array DividersMohamed A. Nadeem, Chandan Kumar Jha 0001, Rolf Drechsler. 1-3 [doi]
• DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAMVictor Cai, Jennifer Zhou, David Brooks 0001, Gu-Yeon Wei. 1-7 [doi]
• MARS: A General GPU Optimization Framework for Merkle-Tree-Enabled CryptographyYaoyun Zhou, Qian Wang. 1-7 [doi]
• Equicore: Accelerating Clebsch-Gordan Tensor Product of Equivariant Neural Networks on FPGAShidi Tang, Chuanzhao Zhang, Ruiqi Chen 0001, Yuxuan Lv, Bruno da Silva 0001, Ming Ling. 1-7 [doi]
• Code Division Multiplexing based Readout Scheme for Spin QubitsJean-Baptiste Casanova, Quentin Schmidt, Baptiste Jadot, Brian Martinez, Xavier Jehl, Franck Badets, Yvain Thonnart. 1-7 [doi]
• HiM: An Autonomous Hardware Accelerator for Solving Boolean Satisfiability Problem with a Heuristic-in-Macro EngineShin Han, Minhyeok Jeong, Yoonmyung Lee. 1-7 [doi]
• ArchE-Q: A DSP-Free Dataflow Accelerator for Quantized Neural Networks in Sensor-Aided Millimeter-Wave Edge ConnectivityArish Sateesan, Ljiljana Simic, Marina Petrova. 1-3 [doi]
• Preemption Threshold Assignment to Improve Schedulability under Memory ConstraintsThilanka Thilakasiri, Matthias Becker 0004. 1-3 [doi]
• CHIME: Chiplet-based Heterogeneous Near-Memory Acceleration for Edge Multimodal LLM InferenceYanru Chen, Runyang Tian, Yue Pan, Zheyu Li, Weihong Xu, Tajana Rosing. 1-7 [doi]
• ReBIT: A ReRAM-Based In-Situ Training Accelerator with Robustness Against StochasticityPeng Dang, Wei Wang, Yintao He, Huawei Li 0001. 1-2 [doi]
• An Open Source Design Exploration Tool for Battery and Coolant ConfigurationFrancesco Tosoni 0002, Yukai Chen, Massimo Poncino, Franco Fummi, Sara Vinco. 1-3 [doi]
• CoMix-D: A Low-Cost, RNG-Free Decorrelator via Correlation Mixing for Stochastic ComputingYexian Lin, Chunyan Wu, Kuncai Zhong, Weikang Qian. 1-3 [doi]
• Adaptive Testing of Compute-in-Memory GANs Using Backpropagation-Guided Test CompactionAnurup Saha, Ashiqur Rasul, Thomas Walton, Amirali Aghazadeh, Abhijit Chatterjee. 1-7 [doi]
• Late Breaking Results: Uncovering the Limits of ECCs in Vision Transformers and a Zero-Cost Reliability EnhancementMohammad Hasan Ahmadilivani, Marten Roots, Marco Restifo, Sven-Markus Loorits, Luca Di Mauro, Jaan Raik. 1-3 [doi]
• Unified Pauli-Rotation Synthesis for Relieving CX-Count Overhead in Tableau-Based Quantum Circuit Optimization FlowYi-Hsiang Kuo, Hsiang-Chun Yang, Hsin-Yu Chen, Chung-Yang Ric Huang. 1-7 [doi]
• FALCON: A Fast and Low-Power Current-Mode Near-Sensor-Computing Architecture for Real-Time Edge Visual ProcessingLiang Zhang, Jing Kou, Jinyao Mi, Yang Liu, Junda Zhao, Junzhan Liu, Wang Kang 0001. 1-3 [doi]
• Dynamic Neural Thresholding on Mixed-Signal Neuromorphic Processors Enabled by Integrated Learning and Hardware DesignKyuseung Han, Kwang-Il Oh, Sukho Lee, Hyeonguk Jang, Jae-Jin Lee, Sooyoung Jang. 1-7 [doi]
• TrainDeeploy: Hardware-Accelerated Parameter-Efficient Fine-Tuning of Small Transformer Models at the Extreme EdgeRun Wang, Victor J. B. Jung, Philip Wiese, Francesco Conti 0001, Alessio Burrello, Luca Benini. 1-7 [doi]
• Glitch Propagation through Flip-Flops Endangers Masking Schemes: Why Time Separation Is RequiredHasin Ishraq Reefat, Mohammad Ebrahimabadi, Sofiane Takarabt, Sylvain Guilley, Naghmeh Karimi. 1-7 [doi]
• Rejection Matters: Efficient Non-Profiling Side-Channel Attack on ML-DSA via Exploiting Public TemplatesYuhan Zhao, Wei Cheng 0003, Zehua Qiao, Yuejun Liu, Yongbin Zhou. 1-7 [doi]
• CaDRO: Causal-Guided Dimensionality Reduction for Scalable Multi-Objective Pareto OptimizationDinithi Jayasuriya, Divake Kumar, Sureshkumar Senthilkumar, Devashri Naik, Nastaran Darabi, Amit Ranjan Trivedi. 1-7 [doi]
• Improving Reliability in Quantized Graph Neural Networks with Node-Wise Entropy-driven Temperature ScalingHadi Mousanejad Jeddi, José L. Núñez-Yáñez. 1-7 [doi]
• DPUConfig: Optimizing ML Inference in FPGAs Using Reinforcement LearningAlexandros Patras, Spyros Lalis, Christos D. Antonopoulos, Nikolaos Bellas. 1-7 [doi]
• UniCircuit: Multimodal Circuit Representation Learning with Anchor-Free AlignmentJingxin Wang, Weikang Qian. 1-3 [doi]
• Fault-tolerance Mapping of Spiking Neural Networks to RRAM-based Neuromorphic HardwareYuqing Xiong, Cao Xiao, Zhijie Yang, Lei Wang, Mengying Zhao. 1-7 [doi]
• Late Breaking Results: Adaptive Ensembles of Dynamic DNNs for Collaborative Edge InferenceMingyu Hu, Amit Kumar Singh 0002, Jonathon S. Hare, Geoff V. Merrett. 1-3 [doi]
• Alternating ZX Circuit Extraction for Hardware-Adaptive CompilationLudwig Schmid, Korbinian Staudacher, Robert Wille. 1-7 [doi]
• Polynomial Verification of 2-Affine SpacesAnna Bernasconi 0001, Valentina Ciriani, Gianmarco Cuciniello, Caroline Dominik, Rolf Drechsler. 1-7 [doi]
• FAST: A Scalable Framework for Accelerating Flexible Structured Sparse TrainingShuaiheng Li, Jun Liu 0117, Xinhao Li, Yaoxiu Lian, Tianlang Zhao, Li Ding 0012, Guohao Dai 0001. 1-2 [doi]
• RAPID: Accelerating Point Cloud Diffusion Models via Space-Aware Mix-Precision QuantizationQichu Sun, Yanan Zhu, Linxi Lu, Haishuang Fan, Jingya Wu, Huawei Li 0001, Xiaowei Li 0001, Guihai Yan. 1-7 [doi]
• Focus Session: Autonomous Systems Dependability in the era of AI: Design Challenges in Safety, Security, Reliability and CertificationBehnaz Ranjbar, Kirankumar Raveendiran, Sudeep Pasricha, Samarjit Chakraborty, Cecilia Carbonelli, Akash Kumar 0001. 1-7 [doi]
• Near-Memory Architecture for Threshold-Ordinal Surface-Based Corner Detection of Event CamerasHongyang Shang, An Guo 0001, Shuai Dong, Junyi Yang, Ye Ke, Arindam Basu. 1-7 [doi]
• Microscaling-Stochastic Computing Based Systolic Arrays for Energy-Efficient Deep Neural Network InferenceMohammad Hassani Sadi, Bilal Hammoud, Norbert Wehn. 1-3 [doi]
• FedTPA: Tackling Data Heterogeneity with Adaptive Parameter Allocation in Federated Instruction TuningYixuan Chen, Jinghui Zhang, Ding Ding. 1-7 [doi]
• Abusing DDS Discovery: Denial-of-Service Attacks Against ROS 2Jiafu Xu, Songran Liu, Zilong Wang, Minghe Yu, Yue Tang, Yang Wang, Weiguang Pang, Wang Yi. 1-3 [doi]
• A Reinforcement Learning Framework for Good Die in Bad Neighborhood AnalysisMohammad Ershad Shaik, Abhishek Kumar Mishra 0002, Nagarajan Kandasamy, Nur A. Touba. 1-7 [doi]
• From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-DesignJinxin Yu, Yudong Pan, Mengdi Wang 0004, Huawei Li 0001, Yinhe Han 0001, Xiaowei Li 0001, Ying Wang 0001. 1-7 [doi]
• Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case StudyYousuf Choudhary, Tosiron Adegbija. 1-3 [doi]
• Multi-Partner Project: dAIEDGE - A Network of Excellence for Distributed, Trustworthy, Efficient and Scalable AI at the EdgeAlain Pagani, José Cano, Haralampos-G. Stratigopoulos, Aysajan Abidin, Mhd Rashed Al Koutayni, Luca Benini, Angelos Bilas, Alessandro Capotondi, Roberto Cavicchioli, Brian Clerkin, Oscar Déniz-Suárez, Margaux Divernois, Baptiste Dupertuis, Dorvan Favre, Giulio Gambardella, Ander García Gangoiti, Carlo Augusto Grazia, Dominik Günzel, Jude Haris, Klodjan K. Hidri, Maïck Huguenin, Manal Jammal, Paul Kling, Christos Kozanitis, Xavier Lessage, Srikanth Mandapati, Philippe Massonet, Alfio Di Mauro, Varesh Mishra, Juan Odriozola, Javier Parra-Domínguez, Nuria Pazos, Viviane Potocnik, Miguel de Prado, Rohit Prasad, Spyridon Raptis, Gregoire Rebstein, Ignacio Sañudo Olmedo, Mohamed Selim, Chinmay Satish Shrivastav, Noelia Vállez, Giorgos Vasiliadis, Micaela Verrucchi, Enrico Vincenzi, Damian Vizár, Devendra Vyas, Stefan Wiehle. 1-7 [doi]
• Late Breaking Results: POSEiDON: Pose Estimation in Dynamic On-device Networks via Hyperdimensional ComputingColin Dupuis, Emilien Meyer, Abu Kaisar Mohammad Masum, Sercan Aygun. 1-3 [doi]
• INSPIRE: In-Sensor Compressed Weight Retrieval for Enhancing ViT Efficiency at EdgeSabbir Ahmed, Deniz Najafi, Mohaiminul Al Nahian, Navid Khoshavi, Abdullah Al Arafat, Mamshad Nayeem Rizve, Mahdi Nikdast, Adnan Siraj Rakin, Shaahin Angizi. 1-7 [doi]
• Consolidating ML-driven Early IR-drop Mitigation for Fast and Reliable IR-drop ClosureMunwon Lee, Chanhee Jeon, Taewhan Kim. 1-7 [doi]
• CHIP-MAP: A Collaborative Optimization Framework for Macro Placement Using Large Language ModelsYiming Du, Renye Yan, Yunfan Yang, Frank Qu, Jiajun Tan, Zhiyu Zheng, Yiming Gan, Ling Liang, Zongwei Wang 0001, YiMao Cai. 1-7 [doi]
• Focus Session: Advanced Hybrid Hardware FuzzingChen Chen 0125, Stephen Muttathil, Mohamadreza Rostami, Nikhilesh Singh, Lichao Wu, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran. 1-7 [doi]
• MinFill: Reinforcement Learning and GNN Guided Reordering for Fill-In Reduction in RF Circuit MatricesHao Zhang, Dan Niu, Cheng Zhuo, Zhou Jin 0001. 1-7 [doi]
• EMaper: Cross-level Electromigration Aware Placement and Routing EDA Workflow for Interconnects Hotspot Prediction and MitigationChenglin Ye, Yuze Lu, Yizhan Liu, Ligong Zhang, Jinghan Xu, Fei Liu, Yibo Lin, Zheng Zhou, Xiaoyan Liu. 1-7 [doi]
• Automated Self-Explanation of Expected versus Perceived Behavior for Interacting Digital SystemsMohammad Alkhiyami, Gianluca Martino, Görschwin Fey. 1-7 [doi]
• DyNAMoE: Dynamic Reconfigurable NoC-based Accelerator for Mixture-of-Expert ModelsMohit Upadhyay, Li-Shiuan Peh. 1-3 [doi]
• EstCoder: A RTL Code Generator based on Static Functional EstimationQi Xiong, Renzhi Chen, Zhigang Fang 0002, Bowei Wang, Yingjie Zhou, Libo Huang 0002, Lei Wang 0011. 1-3 [doi]
• Critical-Path-Centric 3D IC Placement for Timing OptimizationSojung Park, Heechun Park. 1-7 [doi]
• Torrent : A Distributed DMA for Efficient and Flexible Point-to-Multipoint Data MovementYunhao Deng, Fanchen Kong, Xiaoling Yi, Ryan Antonio, Marian Verhelst. 1-7 [doi]
• AO-BFP: An Adaptive Mixed-Precision and Outlier-Aware Block Floating-Point Accelerator for Large Language Model InferenceYifan Wang, Zetao Guo, Wendi Sun, Wenhao Sun, Qiyan Fang, Song Chen 0001, Yi Kang. 1-7 [doi]
• HAWX: A Hardware-Aware FrameWork for Fast and Scalable ApproXimation of DNNsSamira Nazari, Mohammad Saeed Almasi, Mahdi Taheri, Ali Azarpeyvand, Ali Mokhtari, Ali Mahani 0001, Christian Herglotz. 1-7 [doi]
• Fast and Energy-Efficient Support for Low-Precision LLMs on PIMByeori Kim, Sangjun Lee, Eunhyeok Park. 1-7 [doi]
• A Self-Supervised Neuromorphic Processor Using High-Dimensional Representations for Cognitive Map NavigationAnqin Xiao, Luyu Yang, Yuhan He, Hengtan Zhang, Ziyi Yang 0014, Lirong Zheng 0001, Zhuo Zou. 1-7 [doi]
• Multi-Partner Project: A Holistic and Open-Source Approach to Efficient, Secure and Reliable AI Hardware Deployment in DI-EDAIGeorgios Sotiropoulos, Felix Frombach, Julian Höfer, Tanja Harbaum, Jürgen Becker 0001, Henrik Iver Thorøe, Vincent Meyers, Mehdi B. Tahoori, Zeynep Demirdag, Mohammed Bakr Sikal, Hassan Nassar, Heba Khdr, Jörrg Henkel, Christopher Wolters, Philipp van Kempen, Johannes Geier, Ulf Schlichtmann, Batuhan Sesli, Muhammad Sabih, Jakob Wittmann, Frank Hannig, Jürgen Teich, Lukas Steiner, Norbert Wehn, Mohamed Shelkamy Ali, Philipp Schmitz, Wolfgang Kunz, Stefan Koegler, Georg Sigl. 1-7 [doi]
• GANGR: GAN-Assisted Scalable and Efficient Global Routing ParallelizationHadi Khodaei Jooshin, Inna Partin-Vaisband. 1-7 [doi]
• Concurrent Fault Detection for Binary Neural Network Accelerators via On-Chip Voltage MonitoringVincent Meyers, Mahboobe Sadeghipour Roodsari, Mehdi B. Tahoori. 1-7 [doi]
• Automated Hardware Trojan Insertion in Industrial-Scale DesignsYaroslav Popryho, Debjit Pal, Inna Partin-Vaisband. 1-7 [doi]
• GLEAM: A Graph-Learning Enhanced Adaptive Metaheuristic for Power-Aware Scheduling on Heterogeneous Cyber-Physical SystemsAmir Hossein Ansari, Mohsen Ansari, Sepideh Safari, Alireza Ejlali, Jörg Henkel. 1-7 [doi]
• DARE: An Irregularity-Tolerant Matrix Processing Unit with a Densifying ISA and Filtered Runahead ExecutionXin Yang, Xin Fan, Zengshi Wang, Jun Han 0003. 1-7 [doi]
• Timing-Driven Detailed Placement with Collaborative Topology ReconstructionZhengjie Zhao, Wenxin Yu 0001, Jie Ma, Mengshi Gong, Youzhi Zheng, Xinmiao Li, Wenyu Liu, Jingwei Lu. 1-7 [doi]
• From Cloud-Heavy to Edge-Ready: Self-supervised Transfer-efficient Emotion RecognitionJunjiao Sun, José Miranda 0001, Jorge Portilla, Andrés Otero. 1-3 [doi]
• Endor: Exploit Nearly-Decode-Only Opportunities of LLM Reasoning on Near-Memory ArchitectureJun Liu 0117, Tianlang Zhao, Shiyi Liu, Jiancai Ye, Lin Li 0002, Zhen Yu, Li Ding 0012, Hao Zhou 0008, Zhenhua Zhu 0002, Xuefei Ning, Yuan Xie 0001, Yu Wang 0002, Guohao Dai 0001. 1-7 [doi]
• Unlocking Hidden Secrets: Leveraging SRAM Aging Imprints for Sensitive Data RecoveryZakia Tamanna Tisha, Gaines Odom, Biswajit Ray, Ujjwal Guin. 1-3 [doi]
• Explainable Hardware Trojan Detection at RTL using Attention MechanismSiyu Tian, Wei Hu 0008, Lingjuan Wu, Tianle You, Hao Su, Jiacheng Zhu. 1-7 [doi]
• Towards Bit-Shareable Inference on MicrocontrollersCharalampos Bezaitis, Yaman Umuroglu, Di Liu, Magnus Själander. 1-3 [doi]
• Topology-Aware Circuit Breaking on Critical Paths in Microservice SystemsLin Wang, Xin Li 0017, Yanling Bu, Tianhao Zhang, Meiyan Teng, Yanchao Zhao. 1-7 [doi]
• Non-volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V PlatformJiongzhe Su, Mingtao Chen, Zhanpeng Qiu, Bo Liu 0019, Hao Cai 0001. 1-7 [doi]
• Synthesizing Mixed-Mode Operations for Memristors using Majority DecompositionFelix Bayhurst, Li-Wei Chen 0001, Kefeng Li, Heidemarie Krüger, Nan Du 0004, Ilia Polian. 1-3 [doi]
• Fine-Grained Code Analysis for Processor FuzzingZiyue Zheng, Zhi Qu, Yangdi Lyu. 1-7 [doi]
• Khepri: Crystallizing TAGE for Memory Efficient Prewarm in Serverless ComputingZengshi Wang, Zhiyuan Zhang, Zhuoyuan Yang, Kanheng Jiang, Chao Fu, Jun Han 0003. 1-7 [doi]
• An Adaptive Cost-based Via and Congestion Co-optimization Framework for VLSI Global RoutingZhaoyi Wu, Haishan Huang, Jianli Chen, Zhifeng Lin. 1-7 [doi]
• HI-APP: Hardware-friendly Fully-Integer Approximation of Nonlinear Functions in Quantized CLIP-ViTsBeom-Jin Kang, Hyun Kim. 1-7 [doi]
• An Efficient Secure Boot Mechanism Leveraging DICE as a Use CaseUtku Budak, Malek Safieh, Yigit Arda Ozen, Fabrizio De Santis, Georg Sigl. 1-3 [doi]
• Grin: HyperGNN Training Framework for Efficient Edge Inference via Hypergraph RestructuringChaofang Ma, Lin Jiang, ZeYu Li, Xingyu Liu, Jiang Xu 0001, Wei Zhang 0012. 1-7 [doi]
• Unary Positional System: Flexible Balance of Hardware Area and PerformanceZeshi Liu, Zheng Weng, Ruijie Tan, Guangming Tang, Haihang You. 1-7 [doi]
• Braid-ZNS: Leveraging Zone Random Write Area for Efficient In-Storage Compression on ZNS SSDsMinkyu Choi, Joonseong Hwang, Minjin Park, Seokin Hong. 1-3 [doi]
• Efficient Throughput Analysis of Synchronous Dataflow Graphs via Parametric Shortest PathZhengzheng Tian, Mingze Ma, Jian Hou 0002. 1-7 [doi]
• Learning to Sense Without ADCs: Exploiting Phasic Responses from Diffusive MemristorsZhenhang Zhang, Jingang Jin, Ruoyu Zhao, Zixu Wang, Tong Wang, Rui Zuo, J. Joshua Yang, Qinru Qiu. 1-7 [doi]
• Communication-Aware Hybrid Parallelism Mapping for Low-Cost MCM-based DNN AcceleratorsJicheon Kim, Chunmyung Park, Xuan Truong Nguyen, Hyuk-Jae Lee. 1-7 [doi]
• LUT-APP: Dynamic-Precision LUT-based Approximation Unifying Non-Linear Operations in TransformersSeokkyu Yoon, Namjoon Kim, Hyun Kim 0001. 1-7 [doi]
• CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-explorationJinwu Chen, Yuhui Shi, He Wang 0028, Zhe Jiang 0004, Jun Yang 0006, Xin Si, Zhenhua Zhu 0002. 1-7 [doi]
• HGNN-Part: A High-Quality Hypergraph Partitioner Based on Hypergraph Generative ModelShengbo Tong, Rufan Zhou, Chunyan Pei, Wenjian Yu. 1-7 [doi]
• A Reusable Methodology for High-Performance Interconnects using a Standard-Cell based Asynchronous NoC RouterChonghui Zhang, Yizhe Hu, Yi Kang. 1-7 [doi]
• ChipLight: Cross-Layer Optimization of Chiplet Design with Optical Interconnects for LLM TrainingKangbo Bai, Zhantong Zhu, Yifan Ding, Tianyu Jia. 1-7 [doi]
• Boosting LLC Bandwidth Utilization in GPUs through Adaptive Fine-Grained Data MigrationJihun Yoon, Sungbin Jang, Seokin Hong. 1-7 [doi]
• Distilling Graph Reasoning into Lightweight CNNs for Near-Sensor Point Cloud Corruption DetectionGrafika Jati, Martin Molan, Francesco Barchi, Andrea Bartolini, Giuseppe Mercurio, Andrea Acquaviva. 1-7 [doi]
• Bridging the Power Estimation Gap: A GNN-Based Prediction Model for Approximate Logic SynthesisFuxuan Li, Ao Liu, Siting Liu 0001, Hui Wang 0023, Jie Han 0001, Honglan Jiang. 1-7 [doi]
• Enabling Ultra-Reliable Memories: A Practical Framework for Zero Mis-correction SEC-DED-DAEC Codes for Safety-Critical SystemsGuixiang Chen, Sheng Liu 0001, Bo Yuan, Yang Guo 0003. 1-7 [doi]
• Design and Optimization of Mixed-Kernel Mixed-Signal SVMs for Flexible ElectronicsFlorentia Afentaki, Maha Shatta, Konstantinos Balaskas, Georgios Panagopoulos, Georgios Zervakis 0001, Mehdi B. Tahoori. 1-7 [doi]
• QUADOL: A Quality-Driven Approximate Logic Synthesis Method Leveraging Dual-Output LUTs for Modern FPGAsJian Shi, Chang Meng, Xuan Wang 0027, Weikang Qian. 1-7 [doi]
• MetaSyn: A Meta-Reinforcement Learning Framework with Multimodal Circuit Representation for Adaptive Logic SynthesisShukai Liu, Ruoyan Liao, Siyu Wang, Qimin Xu, Cailian Chen. 1-7 [doi]
• CUT-MC: Optimizing the Relationship Between Context Count, Unrolling and Throughput in Multi-Context CGRAsStephen Wicklund, Jason Helge Anderson. 1-3 [doi]
• IMS: Intelligent Hardware Monitoring System for Secure SoCsWadid Foudhaili, Aykut Rencber, Anouar Nechi, Rainer Buchty, Mladen Berekovic, Andres Gomez, Saleh Mulhem. 1-7 [doi]
• Scrooge: Accelerating Attention Inference in LLMs via Early Termination MechanismGwangeun Byeon, Seongwook Kim, Taein Kim, Jungmin Lee, Seokin Hong. 1-7 [doi]
• Focus Session: Hardware/Software Co-Design to Accelerate Generative AI Workloads on Heterogeneous ArchitecturesPratyush Dhingra, Vibhanshu Sharma, Janardhan Rao Doppa, Partha Pratim Pande. 1-7 [doi]
• An Effective SNN Macro with Real-Time STDP and Dynamic LIF Model Based on Thermally Interplayed Spin-Orbit Torque MTJChangyu Li, Linjun Jiang, Liangchen Li, Dehang Zhu, Junda Zhao, Hongxi Liu, Wang Kang 0001, Wenlong Cai, He Zhang 0011, Weisheng Zhao 0001. 1-7 [doi]
• APEX: Integer-only Non-linear Function Approximation for Efficient Cross-Modal InferencePeihuan Ni, Zitao Mo, Tielong Liu, Hongli Wen, Zeyu Zhu, Minnan Pei, Junwen Si, Weifan Guan, Peisong Wang, Qinghao Hu 0001, Gang Li 0015, Jian Cheng 0001. 1-7 [doi]
• ALIFE-BCI: An Adaptive Low-power Integrated Feature Extractor for Brain-Computer InterfacesJoe Saad, Ivan Miro Panades, Adrian Evans, Lorena Anghel. 1-7 [doi]
• A Cluster-Based Distributed Memory Architecture for CGRAsShangkun Li, Cheng Tan 0012, ZeYu Li, Jinming Ge, Jiawei Liang, Hao Yang, Linfeng Du, Jiang Xu 0001, Wei Zhang 0012. 1-3 [doi]
• TEE-based On-demand Key Distribution for Hierarchical In-Vehicle Zonal ArchitectureWonseok Song, Sanghoon Jeon 0005, Jongchan Kim 0001. 1-7 [doi]
• Enabling Cross-Design Power Trace Prediction with GNNs for Gate-Level NetlistsShih-Chun Lin, Yung-Chih Chen, Bo-Hao Huang. 1-7 [doi]
• RIFT: A Single-Bitstream, Runtime-Adaptive FPGA-Based Accelerator for Multimodal AIHyunwoo Oh, Hanning Chen, Sanggeon Yun, Yang Ni 0001, Suyeon Jang, Behnam Khaleghi, Fei Wen, Mohsen Imani. 1-3 [doi]
• Voltage Aware Approximate CGRA Synthesis for Energy Efficient DNN InferenceGeorgios Alexandris, Panagiotis Chaidos, Alexis Maras, Barry de Bruin, Manil Dev Gomony, Henk Corporaal, Dimitrios Soudris, Sotirios Xydis. 1-7 [doi]
• High-Efficiency Neural Beamforming for Real-Time Speech Enhancement on Smart Low-Power Hearable DevicesLuca Bompani, Giovanni Oltrecolli, Marco Fariselli, Francesco Conti 0001. 1-3 [doi]
• SimFuzz: Similarity-guided Block-level Mutation for RISC-V Processor FuzzingHao Lyu, JingZheng Wu, Xiang Ling 0001, Yicheng Zhong, Zhiyuan Li, Tianyue Luo. 1-7 [doi]
• Exploring Heterogeneity-Aware Optimizations for Resource Efficient Edge RecommendationYerin Lee, Gyudong Kim, Eunjin Lee, Jeff Zhang, Young-Ho Gong, Young-geun Kim, Carole-Jean Wu. 1-3 [doi]
• Leveraging Recurrent Patterns in Graph AcceleratorsMasoud Rahimi, Sébastien Le Beux. 1-7 [doi]
• LithoMamba: High-fidelity lithography simulation with State Space ModelsXinyu He, Daohui Wang, Shujing Lyu, Pourya Shamsolmoali, Jiwei Shen, Yue Lu 0001. 1-6 [doi]
• Unified Class and Domain Incremental Learning with Mixture of Experts for Indoor LocalizationAkhil Singampalli, Sudeep Pasricha. 1-7 [doi]
• EGO: Efficient Compression of Unstructured Sparse DNNs for Compute-in-Memory based on Graph Minimum-Cost Matching OptimizationTeng Wan, Yu Cao 0001, Huazhong Yang, Xueqing Li 0002. 1-6 [doi]