Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance - researchr publication related

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Yu Bai, Weidong Kuang. Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance. In 14th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2011, August 31 - September 2, 2011, Oulu, Finland. pages 247-253, IEEE, 2011. [doi]

The following publications are possibly variants of this publication:

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS CircuitsWeidong Kuang, Peiyi Zhao, Jiann S. Yuan, Ronald F. DeMara. tvlsi, 18(3):410-422, 2010. [doi]

Soft Error Hardening for Asynchronous CircuitsWeidong Kuang, Casto Manuel Ibarra, Peiyi Zhao. dft 2007: 273-281 [doi]

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