A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power - researchr publication authors

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Fujun Bai, Baoyu Xiong, Xiaofei Xue, Weizhe Song, Baofeng Wu, Ni Fu, Bing Yu, Huifu Duan, Xiaowei Han, Alessandro Minzoni, Qiwei Ren. A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 426-428, IEEE, 2017. [doi]

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