Fujun Bai, Baoyu Xiong, Xiaofei Xue, Weizhe Song, Baofeng Wu, Ni Fu, Bing Yu, Huifu Duan, Xiaowei Han, Alessandro Minzoni, Qiwei Ren. A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 426-428, IEEE, 2017. [doi]
@inproceedings{BaiXXSWFYDHMR17,
title = {A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power},
author = {Fujun Bai and Baoyu Xiong and Xiaofei Xue and Weizhe Song and Baofeng Wu and Ni Fu and Bing Yu and Huifu Duan and Xiaowei Han and Alessandro Minzoni and Qiwei Ren},
year = {2017},
doi = {10.1109/ASICON.2017.8252504},
url = {https://doi.org/10.1109/ASICON.2017.8252504},
researchr = {https://researchr.org/publication/BaiXXSWFYDHMR17},
cites = {0},
citedby = {0},
pages = {426-428},
booktitle = {12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017},
editor = {Yajie Qin and Zhiliang Hong and Ting-Ao Tang},
publisher = {IEEE},
isbn = {978-1-5090-6625-4},
}