Arindam Banerjee, Debesh Kumar Das. Squarer design with reduced area and delay. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. pages 1-6, IEEE, 2015. [doi]
@inproceedings{BanerjeeD15,
title = {Squarer design with reduced area and delay},
author = {Arindam Banerjee and Debesh Kumar Das},
year = {2015},
doi = {10.1109/ISVDAT.2015.7208092},
url = {http://dx.doi.org/10.1109/ISVDAT.2015.7208092},
researchr = {https://researchr.org/publication/BanerjeeD15},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015},
publisher = {IEEE},
isbn = {978-1-4799-1743-3},
}