A Power and Performance Model for Network-on-Chip Architectures - researchr publication authors

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Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha. A Power and Performance Model for Network-on-Chip Architectures. In 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France. pages 1250-1255, IEEE Computer Society, 2004. [doi]

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