Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond - researchr publication

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Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq. Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. VLSI Syst., 25(5):1669-1680, 2017. [doi]

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