Formal Verification of Timed VHDL Programs - researchr publication authors

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Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Ledu, Emmanuelle Encrenaz, Patricia Renault. Formal Verification of Timed VHDL Programs. In Adam Morawiec, Jinnie Hinderscheit, editors, Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK. pages 80-85, ECSI, Electronic Chips & Systems design Initiative, 2010.

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