Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Ledu, Emmanuelle Encrenaz, Patricia Renault. Formal Verification of Timed VHDL Programs. In Adam Morawiec, Jinnie Hinderscheit, editors, Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK. pages 80-85, ECSI, Electronic Chips & Systems design Initiative, 2010.
@inproceedings{BaraBCLER10,
title = {Formal Verification of Timed VHDL Programs},
author = {Abdelrezzak Bara and Pirouz Bazargan-Sabet and Remy Chevallier and Dominique Ledu and Emmanuelle Encrenaz and Patricia Renault},
year = {2010},
tags = {program verification},
researchr = {https://researchr.org/publication/BaraBCLER10},
cites = {0},
citedby = {0},
pages = {80-85},
booktitle = {Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK},
editor = {Adam Morawiec and Jinnie Hinderscheit},
publisher = {ECSI, Electronic Chips & Systems design Initiative},
}