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H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip

Ian J. Barge, Cristinel Ababei. H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip. In International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017. pages 1-6, IEEE, 2017. [doi]

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