Design Techniques of High Speed PHY using Highly compact FOVEROS Through Silicon Via - researchr publication authors

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Sanjib Basu, Dror Lazar, Rupesh Pothineni. Design Techniques of High Speed PHY using Highly compact FOVEROS Through Silicon Via. In IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022. pages 2542-2546, IEEE, 2022. [doi]

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