A power optimized decimator architecture for cascaded sigma-delta analog-to-digital converters - researchr publication authors

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Markus Becker, Knut Heiber, Maurits Ortmanns, Yiannos Manoli. A power optimized decimator architecture for cascaded sigma-delta analog-to-digital converters. In Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003. pages 798-801, IEEE, 2003. [doi]

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