FPGA based hardware architectures for iterative algorithms implementations - researchr publication authors

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Bogdan Belean, Monica Borda, Adrian Bot. FPGA based hardware architectures for iterative algorithms implementations. In 36th International Conference on Telecommunications and Signal Processing, TSP 2013, Rome, Italy, 2-4 July, 2013. pages 751-754, IEEE, 2013. [doi]

This author has not been identified. Look up 'Bogdan Belean' in GoogleThis author has not been identified. Look up 'Monica Borda' in GoogleThis author has not been identified. Look up 'Adrian Bot' in Google

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