Bogdan Belean, Monica Borda, Adrian Bot. FPGA based hardware architectures for iterative algorithms implementations. In 36th International Conference on Telecommunications and Signal Processing, TSP 2013, Rome, Italy, 2-4 July, 2013. pages 751-754, IEEE, 2013. [doi]
@inproceedings{BeleanBB13,
title = {FPGA based hardware architectures for iterative algorithms implementations},
author = {Bogdan Belean and Monica Borda and Adrian Bot},
year = {2013},
doi = {10.1109/TSP.2013.6614038},
url = {http://dx.doi.org/10.1109/TSP.2013.6614038},
researchr = {https://researchr.org/publication/BeleanBB13},
cites = {0},
citedby = {0},
pages = {751-754},
booktitle = {36th International Conference on Telecommunications and Signal Processing, TSP 2013, Rome, Italy, 2-4 July, 2013},
publisher = {IEEE},
isbn = {978-1-4799-0402-0},
}