Unifying Wire and Time Scheduling for Highlevel Synthesis

Yosi Ben-Asher, Irina Lipov. Unifying Wire and Time Scheduling for Highlevel Synthesis. In 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2018, Hanoi, Vietnam, September 12-14, 2018. pages 28-35, IEEE Computer Society, 2018. [doi]

@inproceedings{Ben-AsherL18,
  title = {Unifying Wire and Time Scheduling for Highlevel Synthesis},
  author = {Yosi Ben-Asher and Irina Lipov},
  year = {2018},
  doi = {10.1109/MCSoC2018.2018.00017},
  url = {https://doi.org/10.1109/MCSoC2018.2018.00017},
  researchr = {https://researchr.org/publication/Ben-AsherL18},
  cites = {0},
  citedby = {0},
  pages = {28-35},
  booktitle = {12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2018, Hanoi, Vietnam, September 12-14, 2018},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5386-6689-0},
}