Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip - researchr publication

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Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Luca Benini. Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(4):623-636, 2016. [doi]

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