33.6 A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS - researchr publication authors

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Mohmad Aasif Bhat, Imon Mondal. 33.6 A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS. In IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, CA, USA, February 15-19, 2026. pages 1-3, IEEE, 2026. [doi]

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