33.6 A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS

Mohmad Aasif Bhat, Imon Mondal. 33.6 A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS. In IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, CA, USA, February 15-19, 2026. pages 1-3, IEEE, 2026. [doi]

@inproceedings{BhatM26,
  title = {33.6 A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS},
  author = {Mohmad Aasif Bhat and Imon Mondal},
  year = {2026},
  doi = {10.1109/ISSCC49663.2026.11409224},
  url = {https://doi.org/10.1109/ISSCC49663.2026.11409224},
  researchr = {https://researchr.org/publication/BhatM26},
  cites = {0},
  citedby = {0},
  pages = {1-3},
  booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, CA, USA, February 15-19, 2026},
  publisher = {IEEE},
  isbn = {979-8-3315-8936-3},
}