Sandeep Bhatia, Niraj K. Jha. Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. on CAD of Integrated Circuits and Systems, 15(2):228-243, 1996. [doi]
@article{BhatiaJ96,
title = {Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability},
author = {Sandeep Bhatia and Niraj K. Jha},
year = {1996},
doi = {10.1109/43.486668},
url = {http://doi.ieeecomputersociety.org/10.1109/43.486668},
tags = {testing},
researchr = {https://researchr.org/publication/BhatiaJ96},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {15},
number = {2},
pages = {228-243},
}