Pritam Bhattacharjee, Alak Majumder. LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. In IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016. pages 250-254, IEEE, 2016. [doi]
@inproceedings{BhattacharjeeM16-0,
title = {LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder},
author = {Pritam Bhattacharjee and Alak Majumder},
year = {2016},
doi = {10.1109/iNIS.2016.064},
url = {https://doi.org/10.1109/iNIS.2016.064},
researchr = {https://researchr.org/publication/BhattacharjeeM16-0},
cites = {0},
citedby = {0},
pages = {250-254},
booktitle = {IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016},
publisher = {IEEE},
isbn = {978-1-5090-6170-9},
}