Table of Contents

• Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit DesignMd. Fahad, Zhou Zhao, Ashok Srivastava, Lu Peng. 1-5 [doi]
• Width-Dependent Characteristics of Graphene Nanoribbon Field Effect Transistor for High Frequency ApplicationsYaser Mohammadi Banadaki, Ashok Srivastava. 6-10 [doi]
• Performance Analysis of Top-Contact MLGNR Based InterconnectsRamesh Kumar, Rohit Dhiman, Rajeevan Chandel. 11-16 [doi]
• Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring SystemsPrabha Sundaravadivel, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka, Himanshu Thapliyal. 17-22 [doi]
• IoT-Based Fall Detection for Smart Home EnvironmentsShalom Greene, Himanshu Thapliyal, David Carpenter. 23-28 [doi]
• Ni-CNT as Isopropanol Sensor: Ab-Initio AnalysisSushmita Dandeliya, Md Shahzad Khan, Anurag Srivastava. 29-33 [doi]
• CMOS-Memristor Hybrid Integrated Pixel SensorsKamilya Smagulova, Aigerim Tankimanova, Alex Pappachen James. 34-37 [doi]
• A Reply Cache Mechanism to Reduce Query Latency of WSN in IoT Sensory EnvironmentYeduri Sreenivasa Reddy, K. K. Pattanaik. 38-42 [doi]
• Design and Implementation of Tunable Bandpass Filter for Biomedical ApplicationsB. K. Saurabh, Nithin Y. B. Kumar, Shivnarayan Patidar, M. H. Vasantha. 43-46 [doi]
• A 4X1 High-Definition Transcranial Direct Current Stimulation Device for Targeting Cerebral Micro Vessels and Functionality Using NIRSGaurav Sharma, Yashika Arora, Shubhajit Roy Chowdhury. 47-51 [doi]
• An Investigation of Power-Performance Aware Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous SystemsPranshu Kalra, Shaista Hussain, Nitin Chaturvedi. 52-55 [doi]
• Securing IEEE 1687 Standard On-chip Instrumentation Access Using PUFSudeendra Kumar K, Naini Satheesh, Abhishek Mahapatra, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra. 56-61 [doi]
• Hardware Security Threats to DSP Applications in an IoT NetworkAzhar Syed, R. Mary Lourde. 62-66 [doi]
• Area and Throughput Analysis of Different AES Architectures for FPGA ImplementationsDisha Yadav, Arvind Rajawat. 67-71 [doi]
• Power Converter Systems for Consumer Electronics DevicesSantanu K. Mishra. 72-75 [doi]
• Graphene Nanoribbon Field Effect Transistor Based Ultra-Low Energy SRAM DesignShital Joshi, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka. 76-79 [doi]
• Protecting Ownership of Reusable IP Core Generated during High Level SynthesisDeepak Kachave, Anirban Sengupta. 80-82 [doi]
• Performance Analysis of Wavy FinFET and Optimization for Leakage ReductionC. Anju, Nisha Kuruvilla, T. E. Ayoob Khan, T. A. Shahul Hameed. 83-88 [doi]
• Novel Ultra Low Leakage FinFET Based SRAM CellVivek Kumar, Vikas Mahor, Manisha Pattanaik. 89-92 [doi]
• Variation Aware Performance Analysis of TFETs for Low-Voltage ComputingVikash Sehwag, Saurav Maji, Mrigank Sharad. 93-97 [doi]
• A Quadro Coding Technique to Reduce Self Transitions in VLSI InterconnectsOjashri Sharma, Aakash Saini, Sandeep Saini, Abhishek Sharma. 98-101 [doi]
• An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock PairPawan Sehgal, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb. 102-107 [doi]
• Parametric Performance Analysis of Synchronous and Asynchronous Heterogeneous Network on ChipAyas Kanta Swain, Anil Kumar Rajput, Kamalakanta Mahapatra. 108-112 [doi]
• Aromaticity Influence on Electron Transport of Molecular Single Electron Transistor: DFT InvestigationBoddepalli Santhi Bhushan, Anurag Srivastava, Jyoti Bhadouria, Rinkoo Bhatia, Pankaj Mishra. 113-117 [doi]
• Proposal of Heterogate Technique for Performance Enhancement of DM-TFETChaitanya Maradana, Jawar Singh. 118-123 [doi]
• Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device ParameterShraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav, Santosh Kumar Vishvakarma. 124-128 [doi]
• Post CMOS Computing Beyond Si: DNA Computer as Future AlternativeMayukh Sarkar, Prasun Ghosal. 129-133 [doi]
• A Provably Good Method to Generate Good DNA SequencesSwapan Shakhari, Prasun Ghosal, Mayukh Sarkar. 134-138 [doi]
• A 60 dB Bulk-Driven Rail-to-Rail Input/Output OTAAbhishek Shrivastava, Ajay Pratap Gangwar, Rahul Kumar, Rohit Dhiman. 139-143 [doi]
• A 0.5V Voltage-Combiner Based Pseudo Differential OTA Design in CMOS Using Weakly Inverted TransistorsAntaryami Panigrahi, Abhipsa Parhi. 144-148 [doi]
• Mixed-Mode Simulation of Common Emitter Amplifier Design Using Bipolar Charge Plasma TransistorChitrakant Sahu, Nitesh Agrawal. 149-154 [doi]
• An Edge Contribution-Based Approach to Identify Influential Nodes from Online Social NetworksSamya Muhuri, Susanta Chakraborty, S. K. Setua. 155-160 [doi]
• Naïve Bayes Approach for Predicting Missing Links in Ego NetworksAnand Kumar Gupta, Neetu Sardana. 161-165 [doi]
• A Neural Network-Based Appliance Scheduling Methodology for Smart Homes and Buildings with Multiple Power SourcesRaj Mani Shukla, Prasanna Kansakar, Arslan Munir. 166-171 [doi]
• Novel FinFET Based Physical Unclonable Functions for Efficient Security Integration in the IoTVenkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos. 172-177 [doi]
• A Modified RO-PUF with Improved Security Metrics on FPGANaini Satheesh, Abhishek Mahapatra, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra. 178-181 [doi]
• TV-PUF: A Fast Lightweight Analog Physical Unclonable FunctionVikash Sehwag, Tanujay Saha. 182-186 [doi]
• A Novel Aging Tolerant RO-PUF for Low Power ApplicationSauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra, Ayas Kanta Swain. 187-192 [doi]
• Turning Software into Hardware - HastlayerZoltan Lehoczky, Richard Toth, Mark Bartha, Andras Retzler, Benedek Farkas, Krisztian Somogyi. 193 [doi]
• Compact Behavioral Modeling and Time Dependent Performance Degradation Analysis of Junction and Doping Free TransistorsMeena Panchore, Jawar Singh, Saraju P. Mohanty, Elias Kougianos. 194-199 [doi]
• Secure Multi-key Generation Using Ring Oscillator Based Physical Unclonable FunctionVenkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos, Jawar Singh. 200-205 [doi]
• Classification of Non-functional Requirements from SRS Documents Using Thematic RolesPrateek Singh, Deepali Singh, Ashish Sharma. 206-207 [doi]
• A Computation Offloading Scheme Leveraging Parameter Tuning for Real-Time IoT DevicesRaj Mani Shukla, Arslan Munir. 208-209 [doi]
• Optical Characteristics of Solution Processed MoO2/ZnO Quantum Dots Based Thin Film TransitorHemant Kumar, Yogesh Kumar, Gopal Rawat, Chandan Kumar, Bhola N. Pal, Satyabrata Jit. 210-213 [doi]
• Electrical and Optical Characteristics of Pd/ZnO Quantum Dots Based Schottky Photodiode on n-SiYogesh Kumar, Hemant Kumr, Gopal Rawat, Chandan Kumar, Bhola N. Pal, S. Jit. 214-217 [doi]
• Design of ESOP-RPLA Array Using DRG2 and DRG4 Gates Based on Reversible Logic TechnologyA. G. Rao, A. K. D. Dwivedi. 218-223 [doi]
• Bid Modification Attack in Smart Grid for Monetary BenefitsKush Khanna, Bijaya Ketan Panigrahi, Anupam Joshi. 224-229 [doi]
• Computing in Ribosomes: Implementing Sequential Circuits Using mRNA-Ribosome SystemPratima Chatterjee, Mayukh Sarkar, Prasun Ghosal. 230-235 [doi]
• Memristor Crossbar-Based Pattern Recognition Circuit Using Perceptron Learning RuleMuhammad Khalid, Jawar Singh. 236-239 [doi]
• Mathematics Using DNA: Performing GCD and LCM on a DNA ComputerMayukh Sarkar, Prasun Ghosal. 240-243 [doi]
• Area and Power-Efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling ApplicationGovinda Sannena, Bishnu Prasad Das. 244-249 [doi]
• LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial AdderPritam Bhattacharjee, Alak Majumder. 250-254 [doi]
• Energy Detection Based Dynamic Spectrum Sensing for 2.4GHz ISM BandSaket Srivastava, Mohammad S. Hashmi, Supratim Das, Dibakar Barua. 255-260 [doi]
• Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETsRituraj Singh Rathore, Rajneesh Sharma, Ashwani K. Rana. 261-263 [doi]
• Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFETNandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma. 264-267 [doi]
• Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM CellAkanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik. 268-273 [doi]
• FinFET-Based Low Power Address Decoder under Process VariationMukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik. 274-277 [doi]
• An Efficient Design Methodology for CNFET Based Ternary Logic CircuitsChetan Vudadha, Sai Phaneendra P., M. B. Srinivas. 278-283 [doi]
• QSCsim - Charge Based Switched Capacitor SimulatorBinsu J. Kailath, Dinesh G.. 284 [doi]