Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis

Sambuddha Bhattacharya, C.-J. Richard Shi. Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. In ISCAS (3). pages 660-663, 2003. [doi]

Authors

Sambuddha Bhattacharya

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C.-J. Richard Shi

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