Sambuddha Bhattacharya, C.-J. Richard Shi. Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. In ISCAS (3). pages 660-663, 2003. [doi]
@inproceedings{BhattacharyaS03c,
title = {Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis},
author = {Sambuddha Bhattacharya and C.-J. Richard Shi},
year = {2003},
doi = {10.1109/ISCAS.2003.1206183},
url = {http://dx.doi.org/10.1109/ISCAS.2003.1206183},
tags = {analysis, C++, algebra, logic},
researchr = {https://researchr.org/publication/BhattacharyaS03c},
cites = {0},
citedby = {0},
pages = {660-663},
booktitle = {ISCAS (3)},
}