Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, Anup Dandapat. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. IEEE Trans. VLSI Syst., 23(10):2001-2008, 2015. [doi]
@article{BhattacharyyaKG15,
title = {Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit},
author = {Partha Bhattacharyya and Bijoy Kundu and Sovan Ghosh and Vinay Kumar and Anup Dandapat},
year = {2015},
doi = {10.1109/TVLSI.2014.2357057},
url = {http://dx.doi.org/10.1109/TVLSI.2014.2357057},
researchr = {https://researchr.org/publication/BhattacharyyaKG15},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {23},
number = {10},
pages = {2001-2008},
}