Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation

Sunitha Bhukya, Bheema Rao Nistala. Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation. Microelectronics Journal, 139:105907, September 2023. [doi]

Authors

Sunitha Bhukya

This author has not been identified. Look up 'Sunitha Bhukya' in Google

Bheema Rao Nistala

This author has not been identified. Look up 'Bheema Rao Nistala' in Google