Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

Levi Bieber, Liwei Wang 0002, Juri Jatskevich, Wei Li 0097. Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters. IEEE Access, 11:4228-4241, 2023. [doi]

@article{BieberWJL23,
  title = {Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters},
  author = {Levi Bieber and Liwei Wang 0002 and Juri Jatskevich and Wei Li 0097},
  year = {2023},
  doi = {10.1109/ACCESS.2023.3235272},
  url = {https://doi.org/10.1109/ACCESS.2023.3235272},
  researchr = {https://researchr.org/publication/BieberWJL23},
  cites = {0},
  citedby = {0},
  journal = {IEEE Access},
  volume = {11},
  pages = {4228-4241},
}