Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

Levi Bieber, Liwei Wang 0002, Juri Jatskevich, Wei Li 0097. Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters. IEEE Access, 11:4228-4241, 2023. [doi]

Abstract

Abstract is missing.