Henry Block, Tsutomu Maruyama. FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm. IEICE Transactions, 100-D(2):256-264, 2017. [doi]
@article{BlockM17,
title = {FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm},
author = {Henry Block and Tsutomu Maruyama},
year = {2017},
url = {http://search.ieice.org/bin/summary.php?id=e100-d_2_256},
researchr = {https://researchr.org/publication/BlockM17},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {100-D},
number = {2},
pages = {256-264},
}