David Boland, George A. Constantinides. An FPGA-based implementation of the MINRES algorithm. In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008. pages 379-384, IEEE, 2008. [doi]
@inproceedings{BolandC08,
title = {An FPGA-based implementation of the MINRES algorithm},
author = {David Boland and George A. Constantinides},
year = {2008},
doi = {10.1109/FPL.2008.4629967},
url = {http://dx.doi.org/10.1109/FPL.2008.4629967},
tags = {rule-based},
researchr = {https://researchr.org/publication/BolandC08},
cites = {0},
citedby = {0},
pages = {379-384},
booktitle = {FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008},
publisher = {IEEE},
}