Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour

Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man. Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. In DAC. pages 513-518, 1989. [doi]

Abstract

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