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A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs

Grzegorz Borowik, Andrzej Krasniewski. A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. In Henry Selvaraj, Dawid Zydek, editors, 21st International Conference on Systems Engineering (ICSEng 2011), Las Vegas, NV, USA, Aug. 16-18, 2011. pages 488-489, IEEE, 2011. [doi]

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