A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Grzegorz Borowik, Andrzej Krasniewski. A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. In Henry Selvaraj, Dawid Zydek, editors, 21st International Conference on Systems Engineering (ICSEng 2011), Las Vegas, NV, USA, Aug. 16-18, 2011. pages 488-489, IEEE, 2011. [doi]

The following publications are possibly variants of this publication:

Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAsGrzegorz Borowik, Andrzej Krasniewski. eurocast 2012: 327-334 [doi]

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAsAndrzej Krasniewski. ddecs 2008: 74-79 [doi]

Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAsAndrzej Krasniewski. dsd 2008: 250-255 [doi]

runs on WebDSL