Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST - researchr publication

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Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie. Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. on CAD of Integrated Circuits and Systems, 18(9):1327-1340, 1999. [doi]

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