Garo Bournoutian, Alex Orailoglu. Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors. In Robert P. Dick, Jan Madsen, editors, Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, part of ESWeek '11 Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011. pages 89-98, ACM, 2011. [doi]
Abstract is missing.