Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe. Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. In 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018. pages 34-42, IEEE Computer Society, 2018. [doi]
Abstract is missing.