Abstract is missing.
- Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking ProtocolsMasashi Imai, Shinichiro Akasaka, Tomohiro Yoneda. 1-8 [doi]
- State Encoding of Asynchronous Controllers Using Pseudo-Boolean OptimizationAlberto Moreno, Jordi Cortadella. 9-16 [doi]
- Partially Systematic Constant-Weight Codes for Delay-Insensitive CommunicationFlorian Huemer, Andreas Steininger. 17-25 [doi]
- Challenges in Building an Open-Source Flow from RTL to Bundled-Data DesignYang Zhang 0014, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel. 26-27 [doi]
- A Design Flow for Shaping Electromagnetic Emissions in Micropipeline CircuitsSophie Germain, Sylvain Engels, Laurent Fesquet. 28-29 [doi]
- Design and Verification of Speed-Independent Circuits with Arbitration in WorkcraftDanil Sokolov, Victor Khomenko, Alex Yakovlev, David Lloyd. 30-31 [doi]
- Loihi Asynchronous Neuromorphic Research ChipAndrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Yi-Hsin Weng, Mike Davies. 32-33 [doi]
- Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous CircuitsAymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe. 34-42 [doi]
- Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial ToolsGhaith Tarawneh, Andrey Mokhov. 43-50 [doi]
- Data-Loop-Free Self-Timed Circuit VerificationCuong K. Chau, Warren A. Hunt Jr., Matt Kaufmann, Marly Roncken, Ivan E. Sutherland. 51-58 [doi]
- Explaining Metastability in Real SynchronizersJustin Reiher, Mark R. Greenstreet, Ian W. Jones. 59-67 [doi]
- Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop ToleranceMatthias Függer, Attila Kinali, Christoph Lenzen, Ben Wiederhake. 68-77 [doi]
- A Serial H-Tree Router for Two-Dimensional ArraysSam Fok, Kwabena Boahen. 78-85 [doi]
- A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD DataChristoph Hoppe, Jens Döge, Peter Reichel, Patrick Russell, Andreas Reichel, Peter Schneider. 86-92 [doi]
- A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip SystemsNing Qiao, Giacomo Indiveri. 93-101 [doi]
- Loadable Kessels CounterOyinkuro Benafa, Danil Sokolov, Alex Yakovlev. 102-109 [doi]
- Static Timing Analysis of Asynchronous Bundled-Data CircuitsGregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet. 110-118 [doi]
- Case Study of Process Variation-Based Domain Partitioning of GPGPUsShomit Das, Michael LeBeane, Bradford M. Beckmann, Greg Sadowski. 119-120 [doi]