Feng Bu, Depeng Sun, Ge Wang, Zonglin Li, Zhou Shu, Bowen Wang 0001, Hao Xu 0005, Na Yan 0004, Ruixue Ding, Shubin Liu 0001, Zhangming Zhu. A 10GHz Double-Edge Sampling PLL with 12.8fsrms Jitter and -257.8dB FoMJ in 65nm CMOS Process. In IEEE Custom Integrated Circuits Conference, CICC 2026, Seattle, WA, USA, April 19-23, 2026. pages 1-4, IEEE, 2026. [doi]
Abstract is missing.