Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Pietro Buccella, Camillo Stefanucci, Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Michel Sallese, Maher Kayal. Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(9):1489-1502, 2016. [doi]

Abstract

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