A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. J. Solid-State Circuits, 58(3):634-646, March 2023. [doi]

Authors

Francesco Buccoleri

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Simone Mattia Dartizio

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Francesco Tesolin

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Luca Avallone

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Alessio Santiccioli

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Agata Iesurum

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Giovanni Steffan

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Dmytro Cherniak

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Luca Bertulessi

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Andrea Bevilacqua

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Carlo Samori

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Andrea L. Lacaita

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Salvatore Levantino

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