A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. J. Solid-State Circuits, 58(3):634-646, March 2023. [doi]

@article{BuccoleriDTASISCBBSLL23,
  title = {A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner},
  author = {Francesco Buccoleri and Simone Mattia Dartizio and Francesco Tesolin and Luca Avallone and Alessio Santiccioli and Agata Iesurum and Giovanni Steffan and Dmytro Cherniak and Luca Bertulessi and Andrea Bevilacqua and Carlo Samori and Andrea L. Lacaita and Salvatore Levantino},
  year = {2023},
  month = {March},
  doi = {10.1109/JSSC.2022.3228899},
  url = {https://doi.org/10.1109/JSSC.2022.3228899},
  researchr = {https://researchr.org/publication/BuccoleriDTASISCBBSLL23},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {58},
  number = {3},
  pages = {634-646},
}