Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs

Betul Buyukkurt, Zhi Guo, Walid A. Najjar. Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. In Koen Bertels, João M. P. Cardoso, Stamatis Vassiliadis, editors, Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers. Volume 3985 of Lecture Notes in Computer Science, pages 401-412, Springer, 2006. [doi]

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