Table of Contents

• Implementation of Realtime and Highspeed Phase Detector on FPGAAndre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner. 1-11 [doi]
• Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable PlatformGerd Van den Branden, Geert Braeckman, Abdellah Touhafi, Erik F. Dirkx. 12-17 [doi]
• Configurable Embedded Core for Controlling Electro-Mechanical SystemsRodrigo Piedade, Leonel Sousa. 18-23 [doi]
• Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded ProcessorsJ. Gonzalez-Gomez, Ivan Gonzalez, Francisco J. Gomez-Arribas, Eduardo I. Boemo. 24-29 [doi]
• Dynamic Partial Reconfigurable FIR Filter DesignYeong-Jae Oh, Hanho Lee, Chong-Ho Lee. 30-35 [doi]
• Event-Driven Simulation Engine for Spiking Neural Networks on a ChipRodrigo Agís, Javier Díaz, Eduardo Ros, Richard R. Carrillo, Eva M. Ortigosa. 36-45 [doi]
• Towards an Optimal Implementation of MLP in FPGAEva M. Ortigosa, Antonio Cañas, R. Rodríguez, Javier Díaz, Sonia Mota. 46-51 [doi]
• Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication ArchitectureKris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips. 52-58 [doi]
• Quality Driven Dynamic Low Power Reconfiguration of HandheldsHiren Joshi, S. S. Verma, G. K. Sharma. 59-64 [doi]
• An Efficient Estimation Method of Dynamic Power Dissipation on VLSI InterconnectsJoong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim. 65-74 [doi]
• Highly Paralellized Architecture for Image Motion EstimationJavier Díaz, Eduardo Ros Vidal, Sonia Mota, Rafael Rodríguez-Gomez. 75-86 [doi]
• Design Exploration of a Video Pre-processor for an FPGA Based SoCNiklas Lepistö, Benny Thörnberg, Mattias O Nils. 87-92 [doi]
• QUKU: A Fast Run Time Reconfigurable Platform for Image Edge DetectionSunil Shukla, Neil W. Bergmann, Jürgen Becker. 93-98 [doi]
• Applications of Small-Scale Reconfigurability to Graphics ProcessorsKevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron. 99-108 [doi]
• An Embedded Multi-camera System for Simultaneous Localization and MappingVanderlei Bonato, José A. de Holanda, Eduardo Marques. 109-114 [doi]
• Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable ProcessorVu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano. 115-121 [doi]
• Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-ChipFrancisco Fons, Mariano Fons, Enrique Cantó, Mariano López. 122-127 [doi]
• Handel-C Design Enhancement for FPGA-Based DV DecoderSlawomir Cichon, Marek Gorgon, Miroslaw Pac. 128-133 [doi]
• Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES PlatformAlex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin. 134-145 [doi]
• A New VLSI Architecture of Lifting-Based DWTYoung-Ho Seo, Dong Wook Kim. 146-151 [doi]
• Architecture Based on FPGA s for Real-Time Image ProcessingIgnacio Bravo, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Ernesto Martín. 152-157 [doi]
• Real Time Image Processing on a Portable Aid Device for Low Vision PatientsEduardo Ros Vidal, Javier Díaz, Sonia Mota, F. Vargas-Martín, M. D. Peláez-Coca. 158-163 [doi]
• General Purpose Real-Time Image Segmentation SystemSonia Mota, Eduardo Ros Vidal, Javier Díaz, Francisco de Toro. 164-169 [doi]
• Implementation of LPM Address Generators on FPGAsHui Qin, Tsutomu Sasao, Jon T. Butler. 170-181 [doi]
• Self Reconfiguring EPIC Soft Core ProcessorsRainer Scholz, Klaus Buchenrieder. 182-186 [doi]
• Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAsSara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos. 187-192 [doi]
• Area/Performance Improvement of NoC ArchitecturesMário P. Véstias, Horácio C. Neto. 193-198 [doi]
• Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input ArrayKwangsup So, Jin-Sang Kim, Won-Kyung Cho, Young-Soo Kim, Doug-Young Suh. 199-204 [doi]
• A Flexible Multi-port Caching Scheme for Reconfigurable PlatformsSu-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk. 205-216 [doi]
• Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode SupportNikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis. 217-229 [doi]
• A Reconfigurable Data Cache for Adaptive ProcessorsDomingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque. 230-242 [doi]
• The Emergence of Non-von Neumann ProcessorsDaniel S. Poznanovic. 243-254 [doi]
• Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task ServerMarcelo Götz, Florian Dittmann. 255-261 [doi]
• A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAsManuel G. Gericota, Gustavo R. Alves, Luís F. Lemos, José M. Ferreira. 262-267 [doi]
• A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIMinoru Watanabe, Fuminori Kobayashi. 268-273 [doi]
• PISC: Polymorphic Instruction Set ComputersStamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz. 274-286 [doi]
• Generic Network Interfaces for Plug and Play NoC Based ArchitectureSanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara. 287-298 [doi]
• Providing QoS Guarantees in a NoC by Virtual Channel ReservationNikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen. 299-310 [doi]
• Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGAMilan Tichý, Jan Schier, David Gregg. 311-316 [doi]
• A Reconfigurable Architecture for MIMO Square Root DecoderHongzhi Wang, Pierre Leray, Jacques Palicot. 317-322 [doi]
• Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password CrackingNele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede. 323-334 [doi]
• Updates on the Security of FPGAs Against Power Analysis AttacksFrançois-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater. 335-346 [doi]
• Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key CryptosystemsKazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede. 347-357 [doi]
• FPGA Implementation of a ::::GF::::(2:::::::m:::::::) Tate Pairing ArchitectureMaurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane. 358-369 [doi]
• Iterative Modular Division over GF(2:::::::m:::::::): Novel Algorithm and Implementations on FPGAGuerric Meurice de Dormale, Jean-Jacques Quisquater. 370-382 [doi]
• Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service ProviderDavid Rodríguez, Juan M. Sánchez, Arturo Duran. 383-388 [doi]
• UNITE: Uniform Hardware-Based Network Intrusion deTection EngineSherif Yusuf, Wayne Luk, M. K. N. Szeto, William G. Osborne. 389-400 [doi]
• Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAsBetul Buyukkurt, Zhi Guo, Walid A. Najjar. 401-412 [doi]
• Automatic Compilation Framework for Bloom Filter Based Intrusion DetectionDinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar. 413-418 [doi]
• A Basic Data Routing Model for a Coarse-Grain Reconfigurable HardwareJie Guo, Gleb Belov, Gerhard Fettweis. 419-424 [doi]
• Hardware and a Tool Chain for ADRESBjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-seok Kim, Suk-Jin Kim. 425-430 [doi]
• Integrating Custom Instruction Specifications into C Development ProcessesJack Whitham, Neil C. Audsley. 431-442 [doi]
• A Compiler-Oriented Architecture Description for Reconfigurable SystemsJens Braunes, Rainer G. Spallek. 443-448 [doi]
• Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software CompatibilityAntonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro. 449-454 [doi]
• High-Level Synthesis Using SPARK and Systolic ArrayJae-Jin Lee, Gi-Yong Song. 455-460 [doi]
• Super Semi-systolic Array-Based Application-Specific PLD ArchitectureJae-Jin Lee, Gi-Yong Song. 461-466 [doi]