FPGA Based Hardware Accelerator Design for Convolution Process in Convolutional Neural Network - researchr publication

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Ardian Dwi C, Trio Adiono, Nana Sutisna. FPGA Based Hardware Accelerator Design for Convolution Process in Convolutional Neural Network. In International Conference on Electrical Engineering and Informatics, ICEEI 2021, Kuala Terengganu, Malaysia, October 12-13, 2021. pages 1-5, IEEE, 2021. [doi]

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