Logic Synthesis for Interpolant Circuit Compaction

Gianpiero Cabodi, Paolo Camurati, Marco Palena, Paolo Pasini, Danilo Vendraminetto. Logic Synthesis for Interpolant Circuit Compaction. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(2):380-384, 2019. [doi]

Authors

Gianpiero Cabodi

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Paolo Camurati

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Marco Palena

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Paolo Pasini

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Danilo Vendraminetto

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