Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze. Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. VLSI Syst., 23(1):142-155, 2015. [doi]
@article{CaiDZYNS15,
title = {Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion},
author = {Yici Cai and Chao Deng and Qiang Zhou and Hailong Yao and Feifei Niu and Cliff N. Sze},
year = {2015},
doi = {10.1109/TVLSI.2014.2300174},
url = {http://dx.doi.org/10.1109/TVLSI.2014.2300174},
researchr = {https://researchr.org/publication/CaiDZYNS15},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {23},
number = {1},
pages = {142-155},
}