Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion

Yici Cai, Chao Deng, Qiang Zhou, Hailong Yao, Feifei Niu, Cliff N. Sze. Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. IEEE Trans. VLSI Syst., 23(1):142-155, 2015. [doi]

Abstract

Abstract is missing.