Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski. Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS. J. Solid-State Circuits, 54(2):550-559, 2019. [doi]

@article{CaiSPMWK19,
  title = {Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS},
  author = {Yunpeng Cai and Anand Savanth and Pranay Prabhat and James Myers and Alex S. Weddell and Tom J. Kazmierski},
  year = {2019},
  doi = {10.1109/JSSC.2018.2875089},
  url = {https://doi.org/10.1109/JSSC.2018.2875089},
  researchr = {https://researchr.org/publication/CaiSPMWK19},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {54},
  number = {2},
  pages = {550-559},
}